#--  Synopsys, Inc.
#--  Version U-2023.03LR-1
#--  Project file D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\rev_3\run_options.txt
#--  Written on Wed Nov 29 09:20:13 2023


#project files
add_file -constraint "D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/source/imp1/timingsdc.sdc"
add_file -verilog "C:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v"
add_file -vhdl -lib pmi "C:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.vhd"
add_file -verilog "C:/lscc/radiant/2023.1/data/reveal/src/ertl/ertl.v"
add_file -verilog "C:/lscc/radiant/2023.1/data/reveal/src/ertl/JTAG_SOFT.v"
add_file -verilog -vlog_std v2001 "D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/imp1/reveal_workspace/tmpreveal/top_la0_trig_gen.v"
add_file -verilog -vlog_std v2001 "D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/imp1/reveal_workspace/tmpreveal/top_la0_gen.v"
add_file -vhdl -lib work "D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/imp1/reveal_workspace/tmpreveal/reveal_coretop.vhd"
add_file -vhdl -lib work "D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/imp1/reveal_workspace/tmpreveal/mysettings.vhd"
add_file -vhdl -lib work "D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/imp1/reveal_workspace/tmpreveal/ce_sync_uniq_0.vhd"
add_file -vhdl -lib work "D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/imp1/reveal_workspace/tmpreveal/cnt_uniq_0.vhd"
add_file -vhdl -lib work "D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/imp1/reveal_workspace/tmpreveal/cnt_uniq_1.vhd"
add_file -vhdl -lib work "D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/imp1/reveal_workspace/tmpreveal/cnt_uniq_2.vhd"
add_file -vhdl -lib work "D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/imp1/reveal_workspace/tmpreveal/cnt_uniq_3.vhd"
add_file -vhdl -lib work "D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/imp1/reveal_workspace/tmpreveal/top.vhd"
add_file -constraint "C:/lscc/radiant/2023.1/data/reveal/src/ertl/reveal_constraint.sdc"


#implementation: "rev_3"
impl -add rev_3 -type fpga

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1
set_option -include_path {D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST}

#device options
set_option -technology LFCPNX
set_option -part LFCPNX_100
set_option -package LFG672C
set_option -speed_grade -9
set_option -part_companion ""

#compilation/mapping options
set_option -top_module "Top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -scm2hydra 0
set_option -scm2hydra_preserve_rtl_sig 1
set_option -hdl_strict_syntax 0
set_option -rtl_xmr_naming 0
set_option -use_module_idb 1

# mapper_without_write_options
set_option -frequency 1
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_structural_verilog 0
set_option -write_vhdl 0

# Lattice XP
set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 1
set_option -forcegsr auto
set_option -fix_gated_and_generated_clocks 0
set_option -rw_check_on_ram 0
set_option -update_models_cp 0
set_option -syn_edif_array_rename 0
set_option -Write_declared_clocks_only 1
set_option -seqshift_no_replicate 0

# Lattice LFCPNX
set_option -s44_optimization 0
set_option -infer_widefn 1
set_option -pack_rst_largeram 1

# NFilter
set_option -no_sequential_opt 0

# common_options
set_option -add_dut_hierarchy 0
set_option -prepare_readback 0

# flow_options
set_option -use_unified_compile 0
set_option -slr_aware_debug 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1

# Compiler Options
set_option -allow_duplicate_modules 1
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_3/top.vm"
impl -active "rev_3"
