Project Settings
Project Name | proj_1 | Device Name | imp1: Lattice LFCPNX : LFCPNX_100
Implementation Name | imp1 | Top Module | Top
Pipelining | 1 | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 1000
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0
Clock Conversion | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 155 | 29 | 0 | - | 00m:11s | - | 2023-11-29 9:20 AM
(premap) | Complete | 5 | 113 | 0 | 0m:00s | 0m:02s | 207MB | 2023-11-29 9:20 AM
(fpga_mapper) | Complete | 15 | 7 | 0 | 0m:00s | 0m:08s | 242MB | 2023-11-29 9:20 AM
Multi-srs Generator | Complete |  |  |  | 00m:01s |  |  | 2023-11-29 9:20 AM
Area Summary
Register bits | 1044 | I/O cells | 5
Block RAMs (v_ram) | 0 | DSPs (dsp_used) | 0
LUTs (total_luts) | 997 |  |
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
CE_Sync_uniq_0|clko_inferred_clock | 1.0 MHz | 396.4 MHz | 997.477
Top|CLK | 1.0 MHz | 223.1 MHz | 995.518
Top|jtck_inferred_clock | 1.0 MHz | 179.4 MHz | 994.426
rvltck | 30.0 MHz | NA | NA
System | 1.0 MHz | 289.0 MHz | 996.539
Optimizations Summary
Combined Clock Conversion | 3 / 0 |  |