@W: MT246 :"d:\02_lscc\09_gsr\final\lab02_prop_circuit_arst\imp1\reveal_workspace\tmpreveal\top.vhd":314:4:314:15|Blackbox JTAGH19 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"d:\02_lscc\09_gsr\final\lab02_prop_circuit_arst\imp1\reveal_workspace\tmpreveal\top.vhd":249:4:249:10|Blackbox OSCA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"d:\02_lscc\09_gsr\final\lab02_prop_circuit_arst\imp1\reveal_workspace\tmpreveal\ce_sync_uniq_0.vhd":23:4:23:8|Blackbox DCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock CE_Sync_uniq_0|clko_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net CE001.CLK1.
@W: MT420 |Found inferred clock Top|jtck_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net jtck.
@W: MT420 |Found inferred clock Top|CLK with period 1000.00ns. Please declare a user-defined clock on net CLK.
@W: MT447 :"c:/lscc/radiant/2023.1/data/reveal/src/ertl/reveal_constraint.sdc":2:0:2:0|Timing constraint (to [get_clocks rvltck]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
