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    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : imp1

    # Written on Wed Nov 29 09:20:30 2023

    ##### DESIGN INFO #######################################################

    Top View:                "Top"
    Constraint File(s):      "D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\source\imp1\timingsdc.sdc"
                             "C:\lscc\radiant\2023.1\data\reveal\src\ertl\reveal_constraint.sdc"

    ##### SUMMARY ############################################################

    Found 1 issues in 1 out of 2 constraints

    ##### DETAILS ############################################################

    Clock Relationships
    *******************

    Starting                               Ending                                 |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                 System                                 |     1000.000         |     No paths         |     No paths         |     No paths
    System                                 Top|jtck_inferred_clock                |     No paths         |     No paths         |     1000.000         |     No paths
    System                                 Top|CLK                                |     1000.000         |     No paths         |     No paths         |     No paths
    CE_Sync_uniq_0|clko_inferred_clock     CE_Sync_uniq_0|clko_inferred_clock     |     1000.000         |     No paths         |     No paths         |     No paths
    CE_Sync_uniq_0|clko_inferred_clock     Top|CLK                                |     Diff grp         |     No paths         |     No paths         |     No paths
    Top|jtck_inferred_clock                System                                 |     No paths         |     No paths         |     No paths         |     1000.000
    Top|jtck_inferred_clock                Top|jtck_inferred_clock                |     No paths         |     1000.000         |     No paths         |     No paths
    Top|jtck_inferred_clock                Top|CLK                                |     No paths         |     No paths         |     No paths         |     Diff grp
    Top|CLK                                System                                 |     1000.000         |     No paths         |     No paths         |     No paths
    Top|CLK                                Top|jtck_inferred_clock                |     No paths         |     No paths         |     Diff grp         |     No paths
    Top|CLK                                Top|CLK                                |     1000.000         |     No paths         |     No paths         |     No paths
    =========================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Unconstrained Start/End Points
    ******************************

    p:LED1
    p:LED2
    p:LED3
    p:LED4
    p:RST_N
    p:TDI
    p:TDO
    p:TMS

    Inapplicable constraints
    ************************

    (none)

    Applicable constraints with issues
    **********************************

    set_false_path -to [get_clocks rvltck]
    	@W::"c:/lscc/radiant/2023.1/data/reveal/src/ertl/reveal_constraint.sdc":2:0:2:0|Timing constraint (to [get_clocks rvltck]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design

    Constraints with matching wildcard expressions
    **********************************************

    (none)

    Library Report
    **************

    # End of Constraint Checker Report

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