    Synthesis Report
    #Build: Synplify Pro (R) U-2023.03LR-1, Build 098R, May 29 2023
    #install: C:\lscc\radiant\2023.1\synpbase
    #OS: Windows 10 or later
    #Hostname: DESKTOP-CQ0R02Q

    # Thu Nov 30 09:29:00 2023

    #Implementation: Async_rst

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : Async_rst
    Synopsys HDL Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N|Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : Async_rst
    Synopsys VHDL Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N|Running in 64-bit mode
    @N:"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd":6:7:6:9|Top entity is set to Top.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reveal_coretop.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\mysettings.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reset_sync_uniq_0.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_0.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_1.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_2.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_3.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd'.
    VHDL syntax check successful!
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reveal_coretop.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\mysettings.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reset_sync_uniq_0.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_0.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_1.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_2.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_3.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd changed - recompiling

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 89MB peak: 89MB)

    Process completed successfully.
    # Thu Nov 30 09:29:01 2023

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : Async_rst
    Synopsys Verilog Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N|Running in 64-bit mode
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\lfcpnx.v" (library work)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":313:13:313:25|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":333:13:333:24|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":92:11:92:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":101:11:101:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v":129:13:129:25|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v":143:13:143:24|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":126:11:126:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":135:11:135:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v":3267:17:3267:29|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v":3274:17:3274:28|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4907:25:4907:37|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4911:25:4911:36|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4942:29:4942:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4946:29:4946:40|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":94:11:94:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":109:11:109:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":210:13:210:25|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":227:13:227:24|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":84:11:84:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":93:11:93:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":91:11:91:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":100:11:100:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":87:11:87:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":96:11:96:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1059:25:1059:37|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1063:25:1063:36|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1094:29:1094:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1098:29:1098:40|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v":146:11:146:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v":155:11:155:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1876:29:1876:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1881:29:1881:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1912:33:1912:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1916:33:1916:44|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1949:29:1949:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1954:29:1954:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1984:33:1984:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1988:33:1988:44|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2504:29:2504:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2509:29:2509:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2540:33:2540:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2544:33:2544:44|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2577:29:2577:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2582:29:2582:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2613:33:2613:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2617:33:2617:44|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3104:29:3104:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3109:29:3109:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3140:33:3140:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3144:33:3144:44|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3177:29:3177:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3182:29:3182:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3213:33:3213:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3217:33:3217:44|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v":1481:25:1481:37|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v":1487:25:1487:36|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v":87:11:87:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v":95:11:95:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v":969:25:969:37|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v":975:25:975:36|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
    @I::"C:\lscc\radiant\2023.1\data\reveal\src\ertl\ertl.v" (library work)
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\ertl.v":242:7:242:17|Net jupdate_int is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\ertl.v":243:7:243:19|Net jupdate_early is not declared.
    @I::"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v" (library work)
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":70:7:70:11|Net JTDIb is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":71:7:71:11|Net JCE1b is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":72:7:72:11|Net JCE2b is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":73:7:73:12|Net JRSTNb is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":74:7:74:13|Net JSHIFTb is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":75:7:75:14|Net JUPDATEb is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":76:7:76:12|Net JRTI1b is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":77:7:77:12|Net JRTI2b is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":78:7:78:11|Net JTCKb is not declared.
    @W: CS141 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":802:28:802:32|Unrecognized synthesis directive state. Verify the correct directive name.
    @I::"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v" (library work)
    @I::"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top_la0_gen.v" (library work)
    Verilog syntax check successful!

    At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)

    Process completed successfully.
    # Thu Nov 30 09:29:02 2023

    ###########################################################]
    ###########################################################[
    @N:"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd":6:7:6:9|Top entity is set to Top.
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reveal_coretop.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\mysettings.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reset_sync_uniq_0.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_0.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_1.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_2.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_3.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd changed - recompiling
    File C:\lscc\radiant\2023.1\synpbase\lib\vhd\signed.vhd changed - recompiling
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reveal_coretop.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\mysettings.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reset_sync_uniq_0.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_0.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_1.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_2.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_3.vhd'.
    @N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd'.
    VHDL syntax check successful!
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reveal_coretop.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\mysettings.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reset_sync_uniq_0.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_0.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_1.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_2.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_3.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd changed - recompiling
    @N: CD630 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd":6:7:6:9|Synthesizing work.top.behave.
    Running optimization stage 1 on OSCA .......
    Finished optimization stage 1 on OSCA (CPU Time 0h:00m:00s, Memory Used current: 92MB peak: 93MB)
    @W: CD638 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd":58:16:58:20|Signal rstni is undriven. Either assign the signal a value or remove the signal declaration.
    @W: CD638 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd":59:11:59:16|Signal clk112 is undriven. Either assign the signal a value or remove the signal declaration.
    @W: CD638 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd":310:11:310:19|Signal reveal_in is undriven. Either assign the signal a value or remove the signal declaration.
    @W: CD638 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top.vhd":311:11:311:20|Signal reveal_out is undriven. Either assign the signal a value or remove the signal declaration.
    @N: CD630 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reveal_coretop.vhd":4:7:4:20|Synthesizing work.reveal_coretop.one.
    @W: CD638 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reveal_coretop.vhd":27:11:27:21|Signal trigger_out is undriven. Either assign the signal a value or remove the signal declaration.
    Running optimization stage 1 on top_la0 .......
    Finished optimization stage 1 on top_la0 (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
    Post processing for work.reveal_coretop.one
    Running optimization stage 1 on reveal_coretop .......
    Finished optimization stage 1 on reveal_coretop (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
    @N: CD630 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_3.vhd":5:7:5:16|Synthesizing work.cnt_uniq_3.rtl.
    @N: CD364 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_3.vhd":95:20:95:24|Removing redundant assignment.
    Post processing for work.cnt_uniq_3.rtl
    Running optimization stage 1 on CNT_uniq_3 .......
    Finished optimization stage 1 on CNT_uniq_3 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
    @N: CD630 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_2.vhd":5:7:5:16|Synthesizing work.cnt_uniq_2.rtl.
    @N: CD364 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_2.vhd":95:20:95:24|Removing redundant assignment.
    Post processing for work.cnt_uniq_2.rtl
    Running optimization stage 1 on CNT_uniq_2 .......
    Finished optimization stage 1 on CNT_uniq_2 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    @N: CD630 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_1.vhd":5:7:5:16|Synthesizing work.cnt_uniq_1.rtl.
    @N: CD364 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_1.vhd":95:20:95:24|Removing redundant assignment.
    Post processing for work.cnt_uniq_1.rtl
    Running optimization stage 1 on CNT_uniq_1 .......
    Finished optimization stage 1 on CNT_uniq_1 (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB)
    @N: CD630 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_0.vhd":5:7:5:16|Synthesizing work.cnt_uniq_0.rtl.
    @N: CD364 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\cnt_uniq_0.vhd":95:20:95:24|Removing redundant assignment.
    Post processing for work.cnt_uniq_0.rtl
    Running optimization stage 1 on CNT_uniq_0 .......
    Finished optimization stage 1 on CNT_uniq_0 (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
    @N: CD630 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\reset_sync_uniq_0.vhd":5:7:5:23|Synthesizing work.reset_sync_uniq_0.rtl.
    Post processing for work.reset_sync_uniq_0.rtl
    Running optimization stage 1 on Reset_Sync_uniq_0 .......
    Finished optimization stage 1 on Reset_Sync_uniq_0 (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
    Post processing for work.top.behave
    Running optimization stage 1 on Top .......
    Finished optimization stage 1 on Top (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB)
    Running optimization stage 2 on Reset_Sync_uniq_0 .......
    Finished optimization stage 2 on Reset_Sync_uniq_0 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB)
    Running optimization stage 2 on CNT_uniq_0_work_top_behave_0layer0 .......
    Finished optimization stage 2 on CNT_uniq_0_work_top_behave_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB)
    Running optimization stage 2 on CNT_uniq_1_work_top_behave_0layer0 .......
    Finished optimization stage 2 on CNT_uniq_1_work_top_behave_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB)
    Running optimization stage 2 on CNT_uniq_2_work_top_behave_0layer0 .......
    Finished optimization stage 2 on CNT_uniq_2_work_top_behave_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB)
    Running optimization stage 2 on CNT_uniq_3_work_top_behave_0layer0 .......
    Finished optimization stage 2 on CNT_uniq_3_work_top_behave_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB)
    Running optimization stage 2 on top_la0 .......
    Finished optimization stage 2 on top_la0 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB)
    Running optimization stage 2 on reveal_coretop .......
    Finished optimization stage 2 on reveal_coretop (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB)
    Running optimization stage 2 on OSCA .......
    Finished optimization stage 2 on OSCA (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB)
    Running optimization stage 2 on Top .......
    Finished optimization stage 2 on Top (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB)

    For a summary of runtime per design unit, please see file:
    ==========================================================
    @L: D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\synwork\layer0.duruntime

    At c_vhdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB)

    Process completed successfully.
    # Thu Nov 30 09:29:04 2023

    ###########################################################]
    ###########################################################[
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\lfcpnx.v" (library work)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":313:13:313:25|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":333:13:333:24|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":92:11:92:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":101:11:101:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v":129:13:129:25|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v":143:13:143:24|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":126:11:126:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":135:11:135:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v":3267:17:3267:29|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v":3274:17:3274:28|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4907:25:4907:37|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4911:25:4911:36|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4942:29:4942:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4946:29:4946:40|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":94:11:94:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":109:11:109:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":210:13:210:25|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":227:13:227:24|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":84:11:84:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":93:11:93:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":91:11:91:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":100:11:100:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":87:11:87:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":96:11:96:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1059:25:1059:37|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1063:25:1063:36|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1094:29:1094:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1098:29:1098:40|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v":146:11:146:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v":155:11:155:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1876:29:1876:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1881:29:1881:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1912:33:1912:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1916:33:1916:44|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1949:29:1949:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1954:29:1954:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1984:33:1984:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1988:33:1988:44|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2504:29:2504:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2509:29:2509:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2540:33:2540:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2544:33:2544:44|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2577:29:2577:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2582:29:2582:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2613:33:2613:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2617:33:2617:44|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3104:29:3104:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3109:29:3109:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3140:33:3140:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3144:33:3144:44|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3177:29:3177:41|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3182:29:3182:40|Read directive translate_on.
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3213:33:3213:45|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3217:33:3217:44|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v":1481:25:1481:37|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v":1487:25:1487:36|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v":87:11:87:23|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v":95:11:95:22|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v" (library work)
    @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v":969:25:969:37|Read directive translate_off.
    @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v":975:25:975:36|Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
    @I::"C:\lscc\radiant\2023.1\data\reveal\src\ertl\ertl.v" (library work)
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\ertl.v":242:7:242:17|Net jupdate_int is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\ertl.v":243:7:243:19|Net jupdate_early is not declared.
    @I::"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v" (library work)
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":70:7:70:11|Net JTDIb is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":71:7:71:11|Net JCE1b is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":72:7:72:11|Net JCE2b is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":73:7:73:12|Net JRSTNb is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":74:7:74:13|Net JSHIFTb is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":75:7:75:14|Net JUPDATEb is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":76:7:76:12|Net JRTI1b is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":77:7:77:12|Net JRTI2b is not declared.
    @W: CG1337 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":78:7:78:11|Net JTCKb is not declared.
    @W: CS141 :"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v":802:28:802:32|Unrecognized synthesis directive state. Verify the correct directive name.
    @I::"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v" (library work)
    @I::"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top_la0_gen.v" (library work)
    Verilog syntax check successful!
    Running optimization stage 1 on rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s .......
    Finished optimization stage 1 on rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s (CPU Time 0h:00m:00s, Memory Used current: 138MB peak: 139MB)
    Running optimization stage 1 on rvl_decode_6s_3s .......
    Finished optimization stage 1 on rvl_decode_6s_3s (CPU Time 0h:00m:00s, Memory Used current: 138MB peak: 139MB)
    Running optimization stage 1 on rvl_tu_1s_0s_0s_0s_1s .......
    Finished optimization stage 1 on rvl_tu_1s_0s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 138MB peak: 139MB)
    Running optimization stage 1 on rvl_tu_16s_0s_0s_0s_1s .......
    Finished optimization stage 1 on rvl_tu_16s_0s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 140MB)
    Running optimization stage 1 on pmi_rtl_ram_dist_64s_6s_2s_reg_none_binary_LFCPNX .......
    Finished optimization stage 1 on pmi_rtl_ram_dist_64s_6s_2s_reg_none_binary_LFCPNX (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 140MB)
    Running optimization stage 1 on rvl_te_Z1_layer1 .......
    Finished optimization stage 1 on rvl_te_Z1_layer1 (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 140MB)
    Running optimization stage 1 on rvl_tcnt_3s_3s_1_0s .......
    Finished optimization stage 1 on rvl_tcnt_3s_3s_1_0s (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
    @N: CG364 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":11:7:11:18|Synthesizing module top_la0_trig in library work.
    Running optimization stage 1 on top_la0_trig .......
    Finished optimization stage 1 on top_la0_trig (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
    Running optimization stage 1 on pmi_rtl_ram_dp_32s_5s_66s_reg_none_binary_LFCPNX .......
    Finished optimization stage 1 on pmi_rtl_ram_dp_32s_5s_66s_reg_none_binary_LFCPNX (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
    Running optimization stage 1 on rvl_tm_Z2_layer1 .......
    Finished optimization stage 1 on rvl_tm_Z2_layer1 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 141MB)
    @N: CG364 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":12:7:12:13|Synthesizing module top_la0 in library work.
    Running optimization stage 1 on top_la0 .......
    Finished optimization stage 1 on top_la0 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 141MB)
    Running optimization stage 2 on top_la0 .......
    @N: CL159 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":61:7:61:13|Input reset_n is unused.
    @N: CL159 :"D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":77:7:77:16|Input trigger_en is unused.
    Finished optimization stage 2 on top_la0 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 141MB)
    Running optimization stage 2 on pmi_rtl_ram_dp_32s_5s_66s_reg_none_binary_LFCPNX .......
    Finished optimization stage 2 on pmi_rtl_ram_dp_32s_5s_66s_reg_none_binary_LFCPNX (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 141MB)
    Running optimization stage 2 on rvl_tm_Z2_layer1 .......
    Finished optimization stage 2 on rvl_tm_Z2_layer1 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 143MB)
    Running optimization stage 2 on top_la0_trig .......
    Finished optimization stage 2 on top_la0_trig (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 143MB)
    Running optimization stage 2 on rvl_tcnt_3s_3s_1_0s .......
    Finished optimization stage 2 on rvl_tcnt_3s_3s_1_0s (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 143MB)
    Running optimization stage 2 on pmi_rtl_ram_dist_64s_6s_2s_reg_none_binary_LFCPNX .......
    Finished optimization stage 2 on pmi_rtl_ram_dist_64s_6s_2s_reg_none_binary_LFCPNX (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 143MB)
    Running optimization stage 2 on rvl_te_Z1_layer1 .......
    Extracted state machine for register next_then_shift
    State machine has 3 reachable states with original encodings of:
       00
       01
       10
    Finished optimization stage 2 on rvl_te_Z1_layer1 (CPU Time 0h:00m:00s, Memory Used current: 144MB peak: 163MB)
    Running optimization stage 2 on rvl_tu_16s_0s_0s_0s_1s .......
    Finished optimization stage 2 on rvl_tu_16s_0s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 163MB)
    Running optimization stage 2 on rvl_tu_1s_0s_0s_0s_1s .......
    Finished optimization stage 2 on rvl_tu_1s_0s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 163MB)
    Running optimization stage 2 on rvl_decode_6s_3s .......
    Finished optimization stage 2 on rvl_decode_6s_3s (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 163MB)
    Running optimization stage 2 on rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s .......
    Finished optimization stage 2 on rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 163MB)

    For a summary of runtime per design unit, please see file:
    ==========================================================
    @L: D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\synwork\layer1.duruntime

    At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 163MB)

    Process completed successfully.
    # Thu Nov 30 09:29:09 2023

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : Async_rst
    Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N|Running in 64-bit mode
    @W: Z198 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top.vhd":322:4:322:10|Unbound component OSCA of instance OSCA001

    =======================================================================================
    For a summary of linker messages for components that did not bind, please see log file:
    @L: D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\synwork\LAB04_Async_rst_comp.linkerlog
    =======================================================================================

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Nov 30 09:29:10 2023

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    @L: D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\synwork\LAB04_Async_rst_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:02s; Memory used current: 23MB peak: 25MB)

    Process took 0h:00m:09s realtime, 0h:00m:02s cputime

    Process completed successfully.
    # Thu Nov 30 09:29:10 2023

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : Async_rst
    Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N|Running in 64-bit mode
    File D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\synwork\LAB04_Async_rst_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Nov 30 09:29:12 2023

    ###########################################################]
    # Thu Nov 30 09:29:12 2023

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : Async_rst
    Synopsys Lattice Technology Pre-mapping, Version map202303lat, Build 070R, Built Jun  8 2023 11:14:23, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 136MB)

    Reading constraint file: D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\timingsdc.sdc
    Reading constraint file: C:\lscc\radiant\2023.1\data\reveal\src\ertl\reveal_constraint.sdc
    @L: D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\LAB04_Async_rst_scck.rpt
    See clock summary report "D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\LAB04_Async_rst_scck.rpt"
    @N: MF916 |Option synthesis_strategy=base is enabled.
    @N: MF248 |Running in 64-bit mode.
    @N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 136MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 148MB peak: 148MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 150MB)

    NConnInternalConnection caching is on
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":119:0:119:7|Instance decode_u of partition view:work.rvl_decode_6s_3s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":133:0:133:3|Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":147:0:147:3|Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":161:0:161:3|Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":175:0:175:3|Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":189:0:189:3|Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":203:0:203:3|Instance tu_5 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":223:0:223:3|Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":264:0:264:3|Instance te_1 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":305:0:305:3|Instance te_2 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":342:0:342:5|Instance tcnt_0 of partition view:work.rvl_tcnt_3s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":119:0:119:7|Instance decode_u of partition view:work.rvl_decode_6s_3s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":133:0:133:3|Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":147:0:147:3|Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":161:0:161:3|Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":175:0:175:3|Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":189:0:189:3|Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":203:0:203:3|Instance tu_5 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":223:0:223:3|Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":264:0:264:3|Instance te_1 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":305:0:305:3|Instance te_2 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":342:0:342:5|Instance tcnt_0 of partition view:work.rvl_tcnt_3s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":119:0:119:7|Instance decode_u of partition view:work.rvl_decode_6s_3s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":133:0:133:3|Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":147:0:147:3|Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":161:0:161:3|Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":175:0:175:3|Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":189:0:189:3|Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":203:0:203:3|Instance tu_5 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":223:0:223:3|Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":264:0:264:3|Instance te_1 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":305:0:305:3|Instance te_2 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":342:0:342:5|Instance tcnt_0 of partition view:work.rvl_tcnt_3s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":110:0:110:9|Instance jtag_int_u of partition view:work.rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":192:0:192:3|Instance tm_u of partition view:work.rvl_tm_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":110:0:110:9|Instance jtag_int_u of partition view:work.rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":192:0:192:3|Instance tm_u of partition view:work.rvl_tm_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":110:0:110:9|Instance jtag_int_u of partition view:work.rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":192:0:192:3|Instance tm_u of partition view:work.rvl_tm_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":119:0:119:7|Instance decode_u of partition view:work.rvl_decode_6s_3s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":133:0:133:3|Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":147:0:147:3|Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":161:0:161:3|Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":175:0:175:3|Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":189:0:189:3|Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":203:0:203:3|Instance tu_5 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":223:0:223:3|Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":264:0:264:3|Instance te_1 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":305:0:305:3|Instance te_2 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":342:0:342:5|Instance tcnt_0 of partition view:work.rvl_tcnt_3s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":119:0:119:7|Instance decode_u of partition view:work.rvl_decode_6s_3s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":133:0:133:3|Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":147:0:147:3|Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":161:0:161:3|Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":175:0:175:3|Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":189:0:189:3|Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":203:0:203:3|Instance tu_5 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":223:0:223:3|Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":264:0:264:3|Instance te_1 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":305:0:305:3|Instance te_2 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":342:0:342:5|Instance tcnt_0 of partition view:work.rvl_tcnt_3s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":119:0:119:7|Instance decode_u of partition view:work.rvl_decode_6s_3s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":133:0:133:3|Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":147:0:147:3|Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":161:0:161:3|Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":175:0:175:3|Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":189:0:189:3|Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":203:0:203:3|Instance tu_5 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":223:0:223:3|Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":264:0:264:3|Instance te_1 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":305:0:305:3|Instance te_2 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":342:0:342:5|Instance tcnt_0 of partition view:work.rvl_tcnt_3s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":119:0:119:7|Instance decode_u of partition view:work.rvl_decode_6s_3s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":133:0:133:3|Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":147:0:147:3|Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":161:0:161:3|Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":175:0:175:3|Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":189:0:189:3|Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":203:0:203:3|Instance tu_5 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":223:0:223:3|Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":264:0:264:3|Instance te_1 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":305:0:305:3|Instance te_2 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":342:0:342:5|Instance tcnt_0 of partition view:work.rvl_tcnt_3s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":119:0:119:7|Instance decode_u of partition view:work.rvl_decode_6s_3s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":133:0:133:3|Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":147:0:147:3|Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":161:0:161:3|Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":175:0:175:3|Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":189:0:189:3|Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":203:0:203:3|Instance tu_5 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":223:0:223:3|Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":264:0:264:3|Instance te_1 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":305:0:305:3|Instance te_2 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_trig_gen.v":342:0:342:5|Instance tcnt_0 of partition view:work.rvl_tcnt_3s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":110:0:110:9|Instance jtag_int_u of partition view:work.rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":192:0:192:3|Instance tm_u of partition view:work.rvl_tm_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":110:0:110:9|Instance jtag_int_u of partition view:work.rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":192:0:192:3|Instance tm_u of partition view:work.rvl_tm_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":110:0:110:9|Instance jtag_int_u of partition view:work.rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s(verilog) has no references to its outputs; instance not removed.
    @W: BN117 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top_la0_gen.v":192:0:192:3|Instance tm_u of partition view:work.rvl_tm_Z2_layer1(verilog) has no references to its outputs; instance not removed.

    Only the first 100 messages of id 'BN117' are reported. To see all messages use 'report_messages -log D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\synlog\LAB04_Async_rst_premap.srr -id BN117' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN117} -count unlimited' in the Tcl shell.

    Starting HSTDM IP insertion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 201MB)

    Finished HSTDM IP insertion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 201MB)

    Started DisTri Cleanup (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 201MB)

    Finished DisTri Cleanup (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 201MB)

    Encoding state machine <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine <encrypted> (in view: work.rvl_te_Z1_layer1_1(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    Encoding state machine <encrypted> (in view: work.rvl_te_Z1_layer1_0(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 203MB peak: 203MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 204MB peak: 204MB)

    @N: FX1184 |Applying syn_allowed_resources blockrams=208 on top level netlist Top

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 204MB peak: 204MB)

    Some data will not be shown as it is part of encrypted module

    Clock Summary
    ******************

              Start                       Requested     Requested     Clock        Clock                     Clock
    Level     Clock                       Frequency     Period        Type         Group                     Load
    --------------------------------------------------------------------------------------------------------------
    0 -       System                      1.0 MHz       1000.000      system       system_clkgroup           0

    0 -       rvltck                      30.0 MHz      33.330        declared     default_clkgroup          0

    0 -       Top|clk150                  1.0 MHz       1000.000      inferred     Inferred_clkgroup_0_1     642

    0 -       Top|jtck_inferred_clock     1.0 MHz       1000.000      inferred     Inferred_clkgroup_0_2     476
    ==============================================================================================================

    Clock Load Summary
    ***********************

                                Clock     Source                         Clock Pin       Non-clock Pin     Non-clock Pin
    Clock                       Load      Pin                            Seq Example     Seq Example       Comb Example
    --------------------------------------------------------------------------------------------------------------------
    System                      0         -                              -               -                 -

    rvltck                      0         TCK(port)                      -               -                 -

    Top|clk150                  642       OSCA001.HFCLKOUT(OSCA)         LED1.C          -                 -

    Top|jtck_inferred_clock     476       jtaghub_inst.JTCK(JTAGH19)     -               -                 -
    ====================================================================================================================

    @W: MT530 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\reset_sync_uniq_0.vhd":17:8:17:9|Found inferred clock Top|clk150 which controls 642 sequential elements including RST001.Rst_Sync. This clock has no specified timing constraint which may adversely impact design performance.

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    2 non-gated/non-generated clock tree(s) driving 1050 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    ============================ Non-Gated/Non-Generated Clocks =============================
    Clock Tree ID     Driving Element       Drive Element Type     Fanout     Sample Instance
    -----------------------------------------------------------------------------------------
    @KP:ckid0_0       jtaghub_inst.JTCK     JTAGH19                476        ENCRYPTED
    @KP:ckid0_1       OSCA001.HFCLKOUT      OSCA                   574        reveal_ist_128
    =========================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    Summary of user generated gated clocks:
    0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)

    @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.

    Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 203MB peak: 204MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 204MB peak: 204MB)

    @W: MF511 |Found issues with constraints. Please check constraint checker report "D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\LAB04_Async_rst_cck.rpt" .

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 206MB peak: 206MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 207MB)

    Process took 0h:00m:02s realtime, 0h:00m:01s cputime
    # Thu Nov 30 09:29:14 2023

    ###########################################################]
    Map & Optimize Report

    # Thu Nov 30 09:29:15 2023

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : Async_rst
    Synopsys Lattice Technology Mapper, Version map202303lat, Build 070R, Built Jun  8 2023 11:14:23, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    @N: MF916 |Option synthesis_strategy=base is enabled.
    @N: MF248 |Running in 64-bit mode.
    @N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 136MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 140MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 203MB peak: 203MB)

    @N: MF179 :"c:\lscc\radiant\2023.1\synpbase\lib\vhd\signed.vhd":114:11:114:29|Found 16 by 16 bit equality operator ('==') op_neq\.un1_CNT1 (in view: work.Top(behave))
    @N: MF179 :"c:\lscc\radiant\2023.1\synpbase\lib\vhd\signed.vhd":114:11:114:29|Found 16 by 16 bit equality operator ('==') op_neq\.un1_CNT2 (in view: work.Top(behave))
    @N: MF179 :"c:\lscc\radiant\2023.1\synpbase\lib\vhd\signed.vhd":114:11:114:29|Found 16 by 16 bit equality operator ('==') op_neq\.un1_CNT3 (in view: work.Top(behave))

    Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 209MB peak: 209MB)

    Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 209MB peak: 210MB)

    Available hyper_sources - for debug and ip models
    	None Found

    NConnInternalConnection caching is on

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 214MB peak: 214MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 215MB peak: 215MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 215MB peak: 215MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 215MB peak: 215MB)

    Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 215MB peak: 215MB)

    Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 217MB peak: 224MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		   993.73ns		1070 /       962

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 218MB peak: 224MB)

    @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Warning: Forcing use of GSR for flip-flops and
    latches that do not specify sets or resets
       CNT01.Couti[15] (in view: work.Top(behave))
       CNT01.Couti[14] (in view: work.Top(behave))
       CNT01.Couti[13] (in view: work.Top(behave))
       CNT01.Couti[12] (in view: work.Top(behave))
       CNT01.Couti[11] (in view: work.Top(behave))
       CNT01.Couti[10] (in view: work.Top(behave))
       CNT01.Couti[9] (in view: work.Top(behave))
       CNT01.Couti[8] (in view: work.Top(behave))
       CNT01.Couti[7] (in view: work.Top(behave))
       CNT01.Couti[6] (in view: work.Top(behave))
       CNT01.Couti[5] (in view: work.Top(behave))
       CNT01.Couti[4] (in view: work.Top(behave))
       CNT01.Couti[3] (in view: work.Top(behave))
       CNT01.Couti[2] (in view: work.Top(behave))
       CNT01.Couti[1] (in view: work.Top(behave))
       CNT01.Couti[0] (in view: work.Top(behave))
       CNT02.Couti[15] (in view: work.Top(behave))
       CNT02.Couti[14] (in view: work.Top(behave))
       CNT02.Couti[13] (in view: work.Top(behave))
       CNT02.Couti[12] (in view: work.Top(behave))
       CNT02.Couti[11] (in view: work.Top(behave))
       CNT02.Couti[10] (in view: work.Top(behave))
       CNT02.Couti[9] (in view: work.Top(behave))
       CNT02.Couti[8] (in view: work.Top(behave))
       CNT02.Couti[7] (in view: work.Top(behave))
       CNT02.Couti[6] (in view: work.Top(behave))
       CNT02.Couti[5] (in view: work.Top(behave))
       CNT02.Couti[4] (in view: work.Top(behave))
       CNT02.Couti[3] (in view: work.Top(behave))
       CNT02.Couti[2] (in view: work.Top(behave))
       CNT02.Couti[1] (in view: work.Top(behave))
       CNT02.Couti[0] (in view: work.Top(behave))
       CNT03.Couti[15] (in view: work.Top(behave))
       CNT03.Couti[14] (in view: work.Top(behave))
       CNT03.Couti[13] (in view: work.Top(behave))
       CNT03.Couti[12] (in view: work.Top(behave))
       CNT03.Couti[11] (in view: work.Top(behave))
       CNT03.Couti[10] (in view: work.Top(behave))
       CNT03.Couti[9] (in view: work.Top(behave))
       CNT03.Couti[8] (in view: work.Top(behave))
       CNT03.Couti[7] (in view: work.Top(behave))
       CNT03.Couti[6] (in view: work.Top(behave))
       CNT03.Couti[5] (in view: work.Top(behave))
       CNT03.Couti[4] (in view: work.Top(behave))
       CNT03.Couti[3] (in view: work.Top(behave))
       CNT03.Couti[2] (in view: work.Top(behave))
       CNT03.Couti[1] (in view: work.Top(behave))
       CNT03.Couti[0] (in view: work.Top(behave))
       CNT04.Couti[15] (in view: work.Top(behave))
       CNT04.Couti[14] (in view: work.Top(behave))
       CNT04.Couti[13] (in view: work.Top(behave))
       CNT04.Couti[12] (in view: work.Top(behave))
       CNT04.Couti[11] (in view: work.Top(behave))
       CNT04.Couti[10] (in view: work.Top(behave))
       CNT04.Couti[9] (in view: work.Top(behave))
       CNT04.Couti[8] (in view: work.Top(behave))
       CNT04.Couti[7] (in view: work.Top(behave))
       CNT04.Couti[6] (in view: work.Top(behave))
       CNT04.Couti[5] (in view: work.Top(behave))
       CNT04.Couti[4] (in view: work.Top(behave))
       CNT04.Couti[3] (in view: work.Top(behave))
       CNT04.Couti[2] (in view: work.Top(behave))
       CNT04.Couti[1] (in view: work.Top(behave))
       CNT04.Couti[0] (in view: work.Top(behave))
       LED1 (in view: work.Top(behave))
       LED2 (in view: work.Top(behave))
       LED3 (in view: work.Top(behave))
       <encrypted> (in view: work.rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s(verilog))
       <encrypted> (in view: work.rvl_jtag_int_66s_66s_0s_0s_7s_66s_66s(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_0(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_1(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_0(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_1(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       reveal_ist_128 (in view: work.Top(behave))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))
       <encrypted> (in view: work.rvl_te_Z1_layer1_2(verilog))

    Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 224MB)

    Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 224MB)

    Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 220MB peak: 224MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 160MB peak: 224MB)

    Writing Analyst data base D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\Async_rst\synwork\LAB04_Async_rst_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 219MB peak: 224MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 224MB)

    @N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 224MB)

    Finished Writing Netlists (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:01s; Memory used current: 222MB peak: 224MB)

    Start final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:01s; Memory used current: 217MB peak: 224MB)

    @W: MT246 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top.vhd":459:4:459:15|Blackbox JTAGH19 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W: MT246 :"d:\02_lscc\09_gsr\final\lab04_hybrid\async_rst\reveal_workspace\tmpreveal\top.vhd":322:4:322:10|Blackbox OSCA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @N: MT615 |Found clock rvltck with period 33.33ns
    @W: MT420 |Found inferred clock Top|clk150 with period 1000.00ns. Please declare a user-defined clock on net clk150.
    @W: MT420 |Found inferred clock Top|jtck_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net jtck.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Thu Nov 30 09:29:23 2023
    #

    Top view:               Top
    Requested Frequency:    1.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):    D:\02_LSCC\09_GSR\Final\LAB04_Hybrid\timingsdc.sdc
                           C:\lscc\radiant\2023.1\data\reveal\src\ertl\reveal_constraint.sdc

    @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: 993.947

                                Requested     Estimated     Requested     Estimated                 Clock        Clock
    Starting Clock              Frequency     Frequency     Period        Period        Slack       Type         Group
    ----------------------------------------------------------------------------------------------------------------------------------
    Top|clk150                  1.0 MHz       257.8 MHz     1000.000      3.879         996.121     inferred     Inferred_clkgroup_0_1
    Top|jtck_inferred_clock     1.0 MHz       165.2 MHz     1000.000      6.053         993.947     inferred     Inferred_clkgroup_0_2
    rvltck                      30.0 MHz      NA            33.330        NA            NA          declared     default_clkgroup
    System                      1.0 MHz       305.5 MHz     1000.000      3.273         996.727     system       system_clkgroup
    ==================================================================================================================================
    Estimated period and frequency reported as NA means no slack depends directly on the clock waveform

    Clock Relationships
    *******************

    Clocks                                            |    rise  to  rise     |    fall  to  fall     |    rise  to  fall     |    fall  to  rise
    ------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                 Ending                   |  constraint  slack    |  constraint  slack    |  constraint  slack    |  constraint  slack
    ------------------------------------------------------------------------------------------------------------------------------------------------
    System                   System                   |  1000.000    996.727  |  No paths    -        |  No paths    -        |  No paths    -
    System                   Top|clk150               |  1000.000    998.270  |  No paths    -        |  No paths    -        |  No paths    -
    System                   Top|jtck_inferred_clock  |  No paths    -        |  No paths    -        |  1000.000    995.650  |  No paths    -
    Top|clk150               System                   |  1000.000    995.896  |  No paths    -        |  No paths    -        |  No paths    -
    Top|clk150               Top|clk150               |  1000.000    996.121  |  No paths    -        |  No paths    -        |  No paths    -
    Top|clk150               Top|jtck_inferred_clock  |  No paths    -        |  No paths    -        |  Diff grp    -        |  No paths    -
    Top|jtck_inferred_clock  System                   |  No paths    -        |  No paths    -        |  No paths    -        |  1000.000    995.024
    Top|jtck_inferred_clock  Top|clk150               |  No paths    -        |  No paths    -        |  No paths    -        |  Diff grp    -
    Top|jtck_inferred_clock  Top|jtck_inferred_clock  |  No paths    -        |  1000.000    993.947  |  No paths    -        |  No paths    -
    ================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: Top|clk150
    ====================================

    Starting Points with Worst Slack
    ********************************

                  Starting                                                         Arrival
    Instance      Reference      Type        Pin     Net                           Time        Slack
                  Clock
    --------------------------------------------------------------------------------------------------
    encrypted     Top|clk150     FD1P3IX     Q       c8pHcEsIxIrb                  0.883       995.895
    encrypted     Top|clk150     FD1P3IX     Q       c8pHcEsIxIrb                  0.883       995.895
    encrypted     Top|clk150     FD1P3IX     Q       c8pHcEsIxIrb                  0.883       995.895
    encrypted     Top|clk150     FD1P3IX     Q       c8pHcEsIxIrb                  0.883       995.895
    encrypted     Top|clk150     FD1P3IX     Q       by1JGvCJzf7h084gCtcbCwbI3     0.838       995.941
    encrypted     Top|clk150     FD1P3IX     Q       by1JGvCJzf7h084gCtcbCwbI3     0.838       995.941
    encrypted     Top|clk150     FD1P3IX     Q       by1JGvCJzf7h084gCtcbCwbI3     0.838       995.941
    encrypted     Top|clk150     FD1P3IX     Q       by1JGvCJzf7h084gCtcbCwbI3     0.838       995.941
    encrypted     Top|clk150     FD1P3IX     Q       zm2EkekIc2usFu3cHrI3          0.838       995.941
    encrypted     Top|clk150     FD1P3IX     Q       zm2EkekIc2usFu3cHrI3          0.838       995.941
    ==================================================================================================

    Ending Points with Worst Slack
    ******************************

                  Starting                                                                 Required
    Instance      Reference      Type        Pin     Net                                   Time         Slack
                  Clock
    -----------------------------------------------------------------------------------------------------------
    encrypted     Top|clk150     WIDEFN9     D1      e1IDB4vm9                             1000.000     995.895
    encrypted     Top|clk150     WIDEFN9     D1      e1IDB4vm9                             1000.000     995.895
    encrypted     Top|clk150     WIDEFN9     D1      e1IDB4vm9                             1000.000     995.895
    encrypted     Top|clk150     WIDEFN9     D1      e1IDB4vm9                             1000.000     995.895
    encrypted     Top|clk150     FD1P3IX     SP      pfam7xdGoKjHfkmkJtvyczgttK7nLwCm7     999.817      996.121
    encrypted     Top|clk150     FD1P3IX     SP      pfam7xdGoKjHfkmkJtvyczgttK7nLwCm7     999.817      996.121
    encrypted     Top|clk150     FD1P3IX     SP      pfam7xdGoKjHfkmkJtvyczgttK7nLwCm7     999.817      996.121
    encrypted     Top|clk150     FD1P3IX     SP      pfam7xdGoKjHfkmkJtvyczgttK7nLwCm7     999.817      996.121
    encrypted     Top|clk150     FD1P3IX     SP      pfam7xdGoKjHfkmkJtvyczgttK7nLwCm7     999.817      996.121
    encrypted     Top|clk150     FD1P3IX     SP      pfam7xdGoKjHfkmkJtvyczgttK7nLwCm7     999.817      996.121
    ===========================================================================================================

    Worst Path Information
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         1000.000

        - Propagation time:                      4.104
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 995.895

        Number of logic level(s):                8
        Starting point:                          encrypted / Q
        Ending point:                            encrypted / D1
        The start point is clocked by            Top|clk150 [rising] (rise=0.000 fall=500.000 period=1000.000) on pin CK
        The end   point is clocked by            System [rising]

    Instance / Net                                 Pin      Pin               Arrival     No. of
    Name                               Type        Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------
    encrypted                          FD1P3IX     Q        Out     0.883     0.883 r     -
    c8pHcEsIxIrb                       Net         -        -       -         -           5
    encrypted                          LUT4        C        In      0.000     0.883 r     -
    encrypted                          LUT4        Z        Out     0.523     1.406 r     -
    da5ho54p4cb2kFtHoyak17             Net         -        -       -         -           1
    encrypted                          LUT4        D        In      0.000     1.406 r     -
    encrypted                          LUT4        Z        Out     0.523     1.929 f     -
    bcCj0hnGbwlAcxGFJcCzcy1FHvgL       Net         -        -       -         -           1
    encrypted                          CCU2        A1       In      0.000     1.929 f     -
    encrypted                          CCU2        COUT     Out     0.784     2.713 r     -
    4eFkhGaaF4d2hcqh5Cdcm8bxvh4Ixn     Net         -        -       -         -           1
    encrypted                          CCU2        CIN      In      0.000     2.713 r     -
    encrypted                          CCU2        COUT     Out     0.059     2.772 r     -
    4eFkhGaaF4d2hcqh5Cdcm8bxvh4I7J     Net         -        -       -         -           1
    encrypted                          CCU2        CIN      In      0.000     2.772 r     -
    encrypted                          CCU2        COUT     Out     0.059     2.831 r     -
    4eFkhGaaF4d2hcqh5Cdcm8bxvh4II3     Net         -        -       -         -           1
    encrypted                          CCU2        CIN      In      0.000     2.831 r     -
    encrypted                          CCU2        COUT     Out     0.059     2.890 r     -
    4eFkhGaaF4d2hcqh5Cdcm8bxvh4Jhn     Net         -        -       -         -           1
    encrypted                          CCU2        CIN      In      0.000     2.890 r     -
    encrypted                          CCU2        S1       Out     0.692     3.582 r     -
    bcCj0hnGbwlAcxGFJcDfs1p4kmCr       Net         -        -       -         -           3
    encrypted                          LUT4        B        In      0.000     3.582 r     -
    encrypted                          LUT4        Z        Out     0.523     4.104 r     -
    e1IDB4vm9                          Net         -        -       -         -           1
    encrypted                          WIDEFN9     D1       In      0.000     4.104 r     -
    ================================================================================================

    ====================================
    Detailed Report for Clock: Top|jtck_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                  Starting                                                         Arrival
    Instance      Reference                   Type        Pin     Net              Time        Slack
                  Clock
    --------------------------------------------------------------------------------------------------
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAemxn       0.996       993.947
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAem23       0.996       993.947
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAem7J       0.986       993.957
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       cmes8uaw9dDn     0.951       994.340
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       cmes8uaw9dI3     0.933       994.357
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAenrJ       0.997       994.468
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAenxn       0.975       994.490
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAemDn       0.951       994.514
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       cmes8uaw9d23     0.923       994.542
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       cmes8uaw9d7J     0.888       994.577
    ==================================================================================================

    Ending Points with Worst Slack
    ******************************

                     Starting                                                                                 Required
    Instance         Reference                   Type        Pin            Net                               Time         Slack
                     Clock
    ------------------------------------------------------------------------------------------------------------------------------
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              eF29acFIhhC9Hpr3ECv               999.789      993.947
    encrypted        Top|jtck_inferred_clock     FD1P3BX     D              iysCylwjcK5ibG7J                  999.789      994.470
    jtaghub_inst     Top|jtck_inferred_clock     JTAGH19     ER2_TDO[0]     er2_tdo0                          1000.000     995.024
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              f2242iptfGG54FCF82lLaCyq0t6rJ     1000.144     995.327
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              f2242iptfGG54FCF82lLaCyq0t6xn     1000.144     995.327
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              f2242iptfGG54FCF82lLaCyq0t6hn     1000.144     995.386
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              f2242iptfGG54FCF82lLaCyq0t6m3     1000.144     995.386
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              cLrLye41nb21F68HzDza23            1000.144     995.654
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              cLrLye41nb21F68HzDzarJ            1000.144     995.712
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              cLrLye41nb21F68HzDzaxn            1000.144     995.712
    ==============================================================================================================================

    Worst Path Information
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.211
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         999.789

        - Propagation time:                      5.843
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     993.947

        Number of logic level(s):                9
        Starting point:                          encrypted / Q
        Ending point:                            encrypted / D
        The start point is clocked by            Top|jtck_inferred_clock [falling] (rise=0.000 fall=500.000 period=1000.000) on pin CK
        The end   point is clocked by            Top|jtck_inferred_clock [falling] (rise=0.000 fall=500.000 period=1000.000) on pin CK

    Instance / Net                                   Pin      Pin               Arrival     No. of
    Name                                 Type        Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------
    encrypted                            FD1P3DX     Q        Out     0.996     0.996 r     -
    umDyvAemxn                           Net         -        -       -         -           54
    encrypted                            LUT4        A        In      0.000     0.996 r     -
    encrypted                            LUT4        Z        Out     0.708     1.704 f     -
    dcByyrora                            Net         -        -       -         -           17
    encrypted                            LUT4        A        In      0.000     1.704 f     -
    encrypted                            LUT4        Z        Out     0.523     2.227 r     -
    dcByyro1A                            Net         -        -       -         -           1
    encrypted                            LUT4        B        In      0.000     2.227 r     -
    encrypted                            LUT4        Z        Out     0.523     2.749 r     -
    fh7pgt                               Net         -        -       -         -           1
    encrypted                            LUT4        A        In      0.000     2.749 r     -
    encrypted                            LUT4        Z        Out     0.523     3.272 r     -
    fh7pgv                               Net         -        -       -         -           1
    encrypted                            LUT4        A        In      0.000     3.272 r     -
    encrypted                            LUT4        Z        Out     0.523     3.796 r     -
    fh7pgx                               Net         -        -       -         -           1
    encrypted                            LUT4        A        In      0.000     3.796 r     -
    encrypted                            LUT4        Z        Out     0.523     4.319 r     -
    dcByyro1C                            Net         -        -       -         -           1
    encrypted                            LUT4        B        In      0.000     4.319 r     -
    encrypted                            LUT4        Z        Out     0.658     4.976 r     -
    hav1h5                               Net         -        -       -         -           6
    encrypted                            LUT4        C        In      0.000     4.976 r     -
    encrypted                            LUT4        Z        Out     0.523     5.500 r     -
    dj4zIgJ5btwfx8BdaF1Gx5lcq3npaDba     Net         -        -       -         -           1
    encrypted                            LUT4        C        In      0.000     5.500 r     -
    encrypted                            LUT4        Z        Out     0.343     5.843 r     -
    eF29acFIhhC9Hpr3ECv                  Net         -        -       -         -           1
    encrypted                            FD1P3DX     D        In      0.000     5.843 r     -
    ==================================================================================================

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                              Starting                                                       Arrival
    Instance                                                                  Reference     Type        Pin              Net                 Time        Slack
                                                                              Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------
    top_reveal_coretop_instance.core0.trig_u.te_1_rd_dout_te_RNI0JCR3[0]      System        WIDEFN9     Z                rd_dout_trig[0]     0.000       995.650
    jtaghub_inst                                                              System        JTAGH19     JCE2             jce2                0.000       997.321
    jtaghub_inst                                                              System        JTAGH19     JSHIFT           jshift              0.000       997.321
    jtaghub_inst                                                              System        JTAGH19     IP_ENABLE[0]     ip_enable[0]        0.000       998.018
    encrypted                                                                 System        WIDEFN9     Z                c7lxGE0D0Hne        0.000       998.270
    top_reveal_coretop_instance.core0.trig_u.tu_4_rd_dout_tu_RNICMPC1[11]     System        WIDEFN9     Z                N_147               0.000       998.755
    top_reveal_coretop_instance.core0.trig_u.tu_4_rd_dout_tu_RNIGQPC1[12]     System        WIDEFN9     Z                N_148               0.000       998.755
    top_reveal_coretop_instance.core0.trig_u.tu_4_rd_dout_tu_RNIKUPC1[13]     System        WIDEFN9     Z                N_149               0.000       998.755
    top_reveal_coretop_instance.core0.trig_u.tu_4_rd_dout_tu_RNIO2QC1[14]     System        WIDEFN9     Z                N_150               0.000       998.755
    jtaghub_inst                                                              System        JTAGH19     JTDI             jtdi                0.000       998.923
    ============================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                     Starting                                                                   Required
    Instance         Reference     Type        Pin            Net                               Time         Slack
                     Clock
    ----------------------------------------------------------------------------------------------------------------
    encrypted        System        FD1P3DX     D              eF29acFIhhC9Hpr3ECv               999.789      995.650
    encrypted        System        FD1P3BX     D              iysCylwjcK5ibG7J                  999.789      996.173
    jtaghub_inst     System        JTAGH19     ER2_TDO[0]     er2_tdo0                          1000.000     996.727
    encrypted        System        FD1P3DX     D              f2242iptfGG54FCF82lLaCyq0t6rJ     1000.144     997.321
    encrypted        System        FD1P3DX     D              f2242iptfGG54FCF82lLaCyq0t6xn     1000.144     997.321
    encrypted        System        FD1P3DX     D              f2242iptfGG54FCF82lLaCyq0t6hn     1000.144     997.380
    encrypted        System        FD1P3DX     D              f2242iptfGG54FCF82lLaCyq0t6m3     1000.144     997.380
    encrypted        System        FD1P3DX     D              bCLf4uIddBmF                      999.789      997.524
    encrypted        System        FD1P3DX     D              bCLf4uIddiDz                      999.789      997.524
    encrypted        System        FD1P3DX     D              bCLf4uIdc2sj                      999.789      997.524
    ================================================================================================================

    Worst Path Information
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.211
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         999.789

        - Propagation time:                      4.139
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 995.650

        Number of logic level(s):                8
        Starting point:                          top_reveal_coretop_instance.core0.trig_u.te_1_rd_dout_te_RNI0JCR3[0] / Z
        Ending point:                            encrypted / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|jtck_inferred_clock [falling] (rise=0.000 fall=500.000 period=1000.000) on pin CK

    Instance / Net                                                                       Pin      Pin               Arrival     No. of
    Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------------------------------
    top_reveal_coretop_instance.core0.trig_u.te_1_rd_dout_te_RNI0JCR3[0]     WIDEFN9     Z        Out     0.000     0.000 r     -
    rd_dout_trig[0]                                                          Net         -        -       -         -           1
    encrypted                                                                LUT4        B        In      0.000     0.000 r     -
    encrypted                                                                LUT4        Z        Out     0.523     0.523 r     -
    dcByyro1A                                                                Net         -        -       -         -           1
    encrypted                                                                LUT4        B        In      0.000     0.523 r     -
    encrypted                                                                LUT4        Z        Out     0.523     1.046 r     -
    fh7pgt                                                                   Net         -        -       -         -           1
    encrypted                                                                LUT4        A        In      0.000     1.046 r     -
    encrypted                                                                LUT4        Z        Out     0.523     1.569 r     -
    fh7pgv                                                                   Net         -        -       -         -           1
    encrypted                                                                LUT4        A        In      0.000     1.569 r     -
    encrypted                                                                LUT4        Z        Out     0.523     2.092 r     -
    fh7pgx                                                                   Net         -        -       -         -           1
    encrypted                                                                LUT4        A        In      0.000     2.092 r     -
    encrypted                                                                LUT4        Z        Out     0.523     2.615 r     -
    dcByyro1C                                                                Net         -        -       -         -           1
    encrypted                                                                LUT4        B        In      0.000     2.615 r     -
    encrypted                                                                LUT4        Z        Out     0.658     3.273 r     -
    hav1h5                                                                   Net         -        -       -         -           6
    encrypted                                                                LUT4        C        In      0.000     3.273 r     -
    encrypted                                                                LUT4        Z        Out     0.523     3.796 r     -
    dj4zIgJ5btwfx8BdaF1Gx5lcq3npaDba                                         Net         -        -       -         -           1
    encrypted                                                                LUT4        C        In      0.000     3.796 r     -
    encrypted                                                                LUT4        Z        Out     0.343     4.139 r     -
    eF29acFIhhC9Hpr3ECv                                                      Net         -        -       -         -           1
    encrypted                                                                FD1P3DX     D        In      0.000     4.139 r     -
    ======================================================================================================================================

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    @W: MT447 :"c:/lscc/radiant/2023.1/data/reveal/src/ertl/reveal_constraint.sdc":2:0:2:0|Timing constraint (to [get_clocks rvltck]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:01s; Memory used current: 218MB peak: 224MB)

    Finished timing report (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:01s; Memory used current: 218MB peak: 224MB)

    ---------------------------------------
    Resource Usage Report
    Part: lfcpnx_100-9

    Register bits: 962 of 79872 (1%)
    PIC Latch:       0
    I/O cells:       6
    Block Rams : 2 of 208 (0%)

    Details:
    CCU2:           166
    DPR16X4:        12
    FD1P3BX:        32
    FD1P3DX:        280
    FD1P3IX:        640
    FD1P3JX:        7
    GSR:            1
    IB:             2
    INV:            13
    JTAGH19:        1
    LUT4:           954
    OB:             4
    OFD1P3IX:       3
    OSCA:           1
    PDP16K:         2
    VHI:            26
    VLO:            26
    WIDEFN9:        42

    Resource Usage inside macros:
    Registers: 0
    LUTs: 0
    EBRs: 0
    LRAMs: 0
    DSPs: 0
    Distributed RAMs: 0
    Carry Chains: 0
    Blackboxes: 0

    Mapping Summary:
    Total number of registers: 962 + 0 = 962 of 79872 (1.20%)
    Total number of LUTs: 954 + 0 = 954
    Total number of EBRs: 2 + 0 = 2 of 208 (0.96%)
    Total number of LRAMs: 0 + 0 = 0 of 7 (0.00%)
    Total number of DSPs: 0 + 0 = 0 of 156 (0.00%)
    Total number of Distributed RAMs: 12 + 0 = 12
    Total number of Carry Chains: 166 + 0 = 166
    Total number of BlackBoxes: 55 + 0 = 55
    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:01s; Memory used current: 73MB peak: 224MB)

    Process took 0h:00m:08s realtime, 0h:00m:02s cputime
    # Thu Nov 30 09:29:23 2023

    ###########################################################]