`

    #Build: Synplify Pro (R) U-2023.03LR-SP1, Build 214R, Oct 17 2023
    #install: C:\lscc\radiant\2023.2\synpbase
    #OS: Windows 10 or later
    #Hostname: DESKTOP-CQ0R02Q

    # Wed Dec 27 09:21:11 2023

    #Implementation: impl_1

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: C:\lscc\radiant\2023.2\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys HDL Compiler, Version comp202303synp1, Build 218R, Built Oct 17 2023 09:25:20, @

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: C:\lscc\radiant\2023.2\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys VHDL Compiler, Version comp202303synp1, Build 218R, Built Oct 17 2023 09:25:20, @

    @N: :  | Running in 64-bit mode
    @N: : DSPtest.vhd(4) | Top entity is set to presubmult.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB06_DSP\source\impl_1\DSPtest.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\cae_library\synthesis\vhdl\lfcpnx.vhd'.
    VHDL syntax check successful!

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)

    Process completed successfully.
    # Wed Dec 27 09:21:11 2023

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: C:\lscc\radiant\2023.2\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys Verilog Compiler, Version comp202303synp1, Build 218R, Built Oct 17 2023 09:25:20, @

    @N: :  | Running in 64-bit mode
    @I::"C:\lscc\radiant\2023.2\synpbase\lib\lucent\lfcpnx.v" (library work)
    @I::"C:\lscc\radiant\2023.2\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\radiant\2023.2\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\radiant\2023.2\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\lscc\radiant\2023.2\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_addsub.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
    @N:CG334 : lscc_add_sub.v(313) | Read directive translate_off.
    @N:CG333 : lscc_add_sub.v(333) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_add.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_add.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_complex_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
    @N:CG334 : pmi_complex_mult.v(92) | Read directive translate_off.
    @N:CG333 : pmi_complex_mult.v(101) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_counter.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
    @N:CG334 : lscc_cntr.v(129) | Read directive translate_off.
    @N:CG333 : lscc_cntr.v(143) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_shift_reg.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
    @N:CG334 : pmi_distributed_shift_reg.v(126) | Read directive translate_off.
    @N:CG333 : pmi_distributed_shift_reg.v(135) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo/rtl\lscc_fifo.v" (library work)
    @N:CG334 : lscc_fifo.v(3267) | Read directive translate_off.
    @N:CG333 : lscc_fifo.v(3274) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo_dc.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo_dc.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v" (library work)
    @N:CG334 : lscc_fifo_dc.v(4905) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4909) | Read directive translate_on.
    @N:CG334 : lscc_fifo_dc.v(4940) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4944) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_mac.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
    @N:CG334 : pmi_mac.v(94) | Read directive translate_off.
    @N:CG333 : pmi_mac.v(109) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsubsum.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
    @N:CG334 : lscc_mult_add_sub_sum.v(210) | Read directive translate_off.
    @N:CG333 : lscc_mult_add_sub_sum.v(227) | Read directive translate_on.
    @N:CG334 : pmi_multaddsubsum.v(84) | Read directive translate_off.
    @N:CG333 : pmi_multaddsubsum.v(93) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsub.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
    @N:CG334 : pmi_multaddsub.v(91) | Read directive translate_off.
    @N:CG333 : pmi_multaddsub.v(100) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
    @N:CG334 : pmi_mult.v(87) | Read directive translate_off.
    @N:CG333 : pmi_mult.v(96) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v" (library work)
    @N:CG334 : lscc_ram_dp.v(1060) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1064) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp.v(1095) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1099) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp_be.v" (library work)
    @N:CG334 : pmi_ram_dp_be.v(146) | Read directive translate_off.
    @N:CG333 : pmi_ram_dp_be.v(155) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp_true.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp_true.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work)
    @N:CG334 : lscc_ram_dp_true.v(1880) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1885) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1916) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1920) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1953) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1958) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1988) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1992) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2508) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2513) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2544) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2548) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2581) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2586) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2617) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2621) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3108) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3113) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3144) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3148) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3181) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3186) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3217) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3221) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dq.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v" (library work)
    @N:CG334 : lscc_ram_dq.v(1485) | Read directive translate_off.
    @N:CG333 : lscc_ram_dq.v(1491) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dq_be.v" (library work)
    @N:CG334 : pmi_ram_dq_be.v(87) | Read directive translate_off.
    @N:CG333 : pmi_ram_dq_be.v(95) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_rom.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/rom/rtl\lscc_rom.v" (library work)
    @N:CG334 : lscc_rom.v(970) | Read directive translate_off.
    @N:CG333 : lscc_rom.v(976) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_sub.v" (library work)
    @I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
    Verilog syntax check successful!

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)

    Process completed successfully.
    # Wed Dec 27 09:21:12 2023

    ###########################################################]
    ###########################################################[
    @N: : DSPtest.vhd(4) | Top entity is set to presubmult.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB06_DSP\source\impl_1\DSPtest.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\cae_library\synthesis\vhdl\lfcpnx.vhd'.
    VHDL syntax check successful!
    @N:CD630 : DSPtest.vhd(4) | Synthesizing work.presubmult.rtl.
    @W:CD638 : DSPtest.vhd(22) | Signal ai is undriven. Either assign the signal a value or remove the signal declaration.
    @W:CD638 : DSPtest.vhd(23) | Signal bi is undriven. Either assign the signal a value or remove the signal declaration.
    @W:CD638 : DSPtest.vhd(24) | Signal ci is undriven. Either assign the signal a value or remove the signal declaration.
    @W:CD638 : DSPtest.vhd(25) | Signal add is undriven. Either assign the signal a value or remove the signal declaration.
    @W:CD638 : DSPtest.vhd(25) | Signal addi is undriven. Either assign the signal a value or remove the signal declaration.
    @W:CD638 : DSPtest.vhd(26) | Signal p is undriven. Either assign the signal a value or remove the signal declaration.
    @W:CD638 : DSPtest.vhd(26) | Signal multi is undriven. Either assign the signal a value or remove the signal declaration.
    @W:CD638 : DSPtest.vhd(26) | Signal pi is undriven. Either assign the signal a value or remove the signal declaration.
    Post processing for work.presubmult.rtl
    Running optimization stage 1 on presubmult .......
    @A:CL282 : DSPtest.vhd(38) | Feedback mux created for signal c[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
    @A:CL282 : DSPtest.vhd(38) | Feedback mux created for signal b[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
    @A:CL282 : DSPtest.vhd(38) | Feedback mux created for signal a[11:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
    Finished optimization stage 1 on presubmult (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB)
    Running optimization stage 2 on presubmult .......
    Finished optimization stage 2 on presubmult (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 106MB)

    For a summary of runtime per design unit, please see file:
    ==========================================================
    Linked File:  layer0.duruntime

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)

    Process completed successfully.
    # Wed Dec 27 09:21:12 2023

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: C:\lscc\radiant\2023.2\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 218R, Built Oct 17 2023 09:25:20, @

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Wed Dec 27 09:21:12 2023

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  Lab06_impl_1_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Wed Dec 27 09:21:13 2023

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: C:\lscc\radiant\2023.2\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 218R, Built Oct 17 2023 09:25:20, @

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Wed Dec 27 09:21:14 2023

    ###########################################################]

`
`

    Premap Report

`
`

    # Wed Dec 27 09:21:14 2023

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: C:\lscc\radiant\2023.2\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys Lattice Technology Pre-mapping, Version map202303lat, Build 169R, Built Oct 17 2023 18:02:47, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 136MB)

    Reading constraint file: D:\02_LSCC\09_GSR\Final\LAB06_DSP\Myconstraints.sdc
    Linked File:  Lab06_impl_1_scck.rpt
    See clock summary report "D:\02_LSCC\09_GSR\Final\LAB06_DSP\impl_1\Lab06_impl_1_scck.rpt"
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 136MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 136MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

    NConnInternalConnection caching is on

    Starting HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)

    Finished HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)

    Started DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)

    Finished DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 195MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 195MB)

    @N:FX1184 :  | Applying syn_allowed_resources blockrams=208 on top level netlist presubmult

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 196MB)

    Clock Summary
    ******************

              Start     Requested     Requested     Clock        Clock                Clock
    Level     Clock     Frequency     Period        Type         Group                Load
    ---------------------------------------------------------------------------------------
    0 -       clk       200.0 MHz     5.000         declared     default_clkgroup     77
    =======================================================================================

    Clock Load Summary
    ***********************

              Clock     Source        Clock Pin       Non-clock Pin     Non-clock Pin
    Clock     Load      Pin           Seq Example     Seq Example       Comb Example
    ---------------------------------------------------------------------------------
    clk       77        clk(port)     a[11:0].C       -                 -
    =================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    1 non-gated/non-generated clock tree(s) driving 77 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       clk                 port                   77         mult[32:0]
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    Summary of user generated gated clocks:
    0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)

    Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 198MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Dec 27 09:21:15 2023

    ###########################################################]

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    Map & Optimize Report

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    # Wed Dec 27 09:21:16 2023

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-SP1
    Install: C:\lscc\radiant\2023.2\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys Lattice Technology Mapper, Version map202303lat, Build 169R, Built Oct 17 2023 18:02:47, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 192MB)

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)

    Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 197MB)

    Available hyper_sources - for debug and ip models
    	None Found

    NConnInternalConnection caching is on

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 223MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 223MB peak: 224MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 224MB)

    Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 224MB)

    Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 224MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:02s		100000.00ns		   1 /         0

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 225MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 225MB)

    Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 225MB)

    Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 224MB peak: 225MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 172MB peak: 225MB)

    Writing Analyst data base D:\02_LSCC\09_GSR\Final\LAB06_DSP\impl_1\synwork\Lab06_impl_1_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:04s; Memory used current: 225MB peak: 225MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:04s; Memory used current: 227MB peak: 227MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:04s; Memory used current: 227MB peak: 227MB)

    Finished Writing Netlists (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:04s; Memory used current: 227MB peak: 227MB)

    Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:04s; Memory used current: 223MB peak: 227MB)

    @W:MT246 : std.vhd(12) | Blackbox MULTPREADD18X18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @N:MT615 :  | Found clock clk with period 5.00ns

    ##### START OF TIMING REPORT #####[
    # Timing report written on Wed Dec 27 09:21:24 2023
    #

    Top view:               presubmult
    Requested Frequency:    200.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):    D:\02_LSCC\09_GSR\Final\LAB06_DSP\Myconstraints.sdc

    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: NA

                       Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group
    ------------------------------------------------------------------------------------------------------------------
    clk                200.0 MHz     NA            5.000         NA            NA        declared     default_clkgroup
    System             200.0 MHz     NA            5.000         NA            NA        system       system_clkgroup
    ==================================================================================================================
    Estimated period and frequency reported as NA means no slack depends directly on the clock waveform

    Clock Relationships
    *******************

    Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    --------------------------------------------------------------------------------------------------------
    Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    --------------------------------------------------------------------------------------------------------
    ========================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:04s; Memory used current: 224MB peak: 227MB)

    Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:04s; Memory used current: 224MB peak: 227MB)

    ---------------------------------------
    Resource Usage Report
    Part: lfcpnx_100-9

    Register bits: 0 of 79872 (0%)
    PIC Latch:       0
    I/O cells:       79

    DSP primitives:       1 of 468 (0%)

    Details:
    GSR:            1
    IB:             46
    INV:            1
    MULTPREADD18X18: 1
    OB:             33
    VHI:            1
    VLO:            1

    Resource Usage inside macros:
    Registers: 0
    LUTs: 0
    EBRs: 0
    LRAMs: 0
    DSPs: 0
    Distributed RAMs: 0
    Carry Chains: 0
    Blackboxes: 0

    Mapping Summary:
    Total number of registers: 0 + 0 = 0 of 79872 (0.00%)
    Total number of LUTs: 0 + 0 = 0
    Total number of EBRs: 0 + 0 = 0 of 208 (0.00%)
    Total number of LRAMs: 0 + 0 = 0 of 7 (0.00%)
    Total number of DSPs: 1 + 0 = 1 of 156 (0.64%)
    Total number of Distributed RAMs: 0 + 0 = 0
    Total number of Carry Chains: 0 + 0 = 0
    Total number of BlackBoxes: 3 + 0 = 3
    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:04s; Memory used current: 87MB peak: 227MB)

    Process took 0h:00m:08s realtime, 0h:00m:04s cputime
    # Wed Dec 27 09:21:24 2023

    ###########################################################]

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