@W: MT246 :"d:\02_lscc\09_gsr\final\lab03_sync_rst\async_rst\reveal_workspace\tmpreveal\top.vhd":446:4:446:15|Blackbox JTAGH19 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"d:\02_lscc\09_gsr\final\lab03_sync_rst\async_rst\reveal_workspace\tmpreveal\top.vhd":313:4:313:10|Blackbox OSCA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock Top|clk150 with period 1000.00ns. Please declare a user-defined clock on net clk150.
@W: MT420 |Found inferred clock Top|jtck_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net jtck.
