    Synthesis Report
    synthesis:  version Radiant Software (64-bit) 2023.1.1.200.1

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.
    Tue Nov 21 18:13:30 2023

    Command Line:  C:\lscc\radiant\2023.1\ispfpga\bin\nt64\synthesis.exe -f LAB07_impl_1_lattice.synproj -gui -msgset D:/02_LSCC/09_GSR/Final/LAB07_Logic_Opt/LAB07/promote.xml

    Synthesis options:
    The -a option is LFCPNX.
    The -t option is ASG256.
    The -sp option is 9_High-Performance_1.0V.
    The -p option is LFCPNX-100.

    ##########################################################

    ### Lattice Family     : LFCPNX

    ### Device             : LFCPNX-100

    ### Package            : ASG256

    ### Performance Grade  : 9_High-Performance_1.0V

    INFO <35001786> - synthesis: User-Selected Strategy Settings
    Optimization goal = Timing
    Top-level module name = Top.
    Target frequency = 200.000000 MHz.
    Maximum fanout = 1000.
    Timing path count = 3 (default)
    BRAM utilization = 100.000000 %
    DSP usage = true
    DSP utilization = 100.000000 %
    fsm_encoding_style = auto
    resolve_mixed_drivers = 0
    fix_gated_clocks = 1

    Mux style = auto (Default)
    Use Carry Chain = true
    carry_chain_length = 0
    Loop Limit = 1950.
    Use IO Insertion = TRUE
    Use IO Reg = AUTO

    Resource Sharing = TRUE
    Propagate Constants = TRUE
    Remove Duplicate Registers = TRUE
    force_gsr = yes
    Output HDL file name = LAB07_impl_1.vm.
    ROM style = auto
    RAM style = auto
    The -comp option is FALSE.
    The -syn option is FALSE.
    Hardtimer checking is enabled (default). The -dt option is not used.
    -path C:/lscc/radiant/2023.1/ispfpga/jd5d00/data (searchpath added)
    -path D:/02_LSCC/09_GSR/Final/LAB07_Logic_Opt/LAB07 (searchpath added)
    -path D:/02_LSCC/09_GSR/Final/LAB07_Logic_Opt/LAB07/impl_1 (searchpath added)
    Mixed language design
    Verilog design file = C:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v
    VHDL library = pmi
    VHDL design file = C:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.vhd
    VHDL library = work
    VHDL design file = D:/02_LSCC/09_GSR/Final/LAB07_Logic_Opt/LAB07/source/impl_1/Reset_Sync.vhd
    The -r option is OFF. [ Remove LOC Properties is OFF. ]
    WARNING <35935050> - synthesis: input port MBISTCLK is not connected on this instance. VDB-5050
    Compile design.
    Compile Design Begin
    Analyzing Verilog file c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v. VERI-1482
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(1): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_addsub.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_addsub.v(40): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/adder_subtractor/rtl/lscc_add_sub.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(2): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_add.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_add.v(50): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/adder/rtl/lscc_adder.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(3): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_complex_mult.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_complex_mult.v(52): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/complex_mult/rtl/lscc_complex_mult.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(4): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_counter.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_counter.v(39): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/counter/rtl/lscc_cntr.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(5): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_dpram.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_dpram.v(43): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/distributed_dpram/rtl/lscc_distributed_dpram.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(6): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_spram.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_spram.v(42): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/distributed_spram/rtl/lscc_distributed_spram.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(7): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_rom.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_rom.v(42): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/distributed_rom/rtl/lscc_distributed_rom.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(8): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_shift_reg.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_shift_reg.v(41): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/ram_shift_reg/rtl/lscc_shift_register.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(9): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_fifo.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_fifo.v(44): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/fifo/rtl/lscc_fifo.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(10): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_fifo_dc.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_fifo_dc.v(47): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/fifo_dc/rtl/lscc_fifo_dc.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(11): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_mac.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_mac.v(52): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/mult_accumulate/rtl/lscc_mult_accumulate.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(12): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_multaddsubsum.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_multaddsubsum.v(53): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/mult_add_sub_sum/rtl/lscc_mult_add_sub_sum.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(13): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_multaddsub.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_multaddsub.v(52): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/mult_add_sub/rtl/lscc_mult_add_sub.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(14): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_mult.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_mult.v(51): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/multiplier/rtl/lscc_multiplier.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(15): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp.v(48): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/ram_dp/rtl/lscc_ram_dp.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(16): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp_be.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp_be.v(49): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/ram_dp/rtl/lscc_ram_dp.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(17): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp_true.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp_true.v(49): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/ram_dp_true/rtl/lscc_ram_dp_true.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(18): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dq.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dq.v(45): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/ram_dq/rtl/lscc_ram_dq.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(19): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dq_be.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dq_be.v(45): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/ram_dq/rtl/lscc_ram_dq.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(20): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_rom.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_rom.v(45): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/rom/rtl/lscc_rom.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(21): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_sub.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_sub.v(50): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/subtractor/rtl/lscc_subtractor.v. VERI-1328
    Analyzing VHDL file c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.vhd. VHDL-1481
    Analyzing VHDL file c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.vhd

    INFO <35921014> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.vhd(4): analyzing package components. VHDL-1014
    Analyzing VHDL file d:/02_lscc/09_gsr/final/lab07_logic_opt/lab07/source/impl_1/reset_sync.vhd. VHDL-1481
    Analyzing VHDL file d:/02_lscc/09_gsr/final/lab07_logic_opt/lab07/source/impl_1/reset_sync.vhd

    INFO <35921012> - synthesis: d:/02_lscc/09_gsr/final/lab07_logic_opt/lab07/source/impl_1/reset_sync.vhd(6): analyzing entity top. VHDL-1012
    INFO <35921010> - synthesis: d:/02_lscc/09_gsr/final/lab07_logic_opt/lab07/source/impl_1/reset_sync.vhd(14): analyzing architecture rtl. VHDL-1010
    INFO <35921504> - synthesis: The default VHDL library search path is now "D:/02_LSCC/09_GSR/Final/LAB07_Logic_Opt/LAB07/impl_1". VHDL-1504
    Top module language type = VHDL.
    Top module name (VHDL, mixed language): Top

    ### Number of Logic Cells: 79872

    ### Number of RAM Blocks: 208

    ### Number of DSP Blocks: 1287

    ### Number of PLLs: 4

    ### Number of IO Pins: 299

    ##########################################################

    CRITICAL <35002028> - synthesis: I/O Port RST 's net has no driver and is unused.

    CRITICAL <35002028> - synthesis: I/O Port RST 's net has no driver and is unused.
    GSR will not be inferred because no asynchronous signal was found in the netlist.
    Applying 200.000000 MHz constraint to all clocks

    Starting design annotation....
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

    Starting full timing analysis...
    Starting design annotation....
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

    Starting full timing analysis...
    Starting design annotation....
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

    Starting full timing analysis...
    Starting design annotation....
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

    Starting full timing analysis...
    WARNING <35935047> - synthesis: Unused instance GSR_INST is removed. VDB-5047

    Area Report

    ################### Begin Area Report (Top)######################
    Number of register bits => 24 of 79872 (0 % )
    FD1P3DX => 16
    FD1P3JX => 8
    GSR => 1
    IB => 17
    OB => 8
    ################### End Area Report ##################
    Number of odd-length carry chains : 0
    Number of even-length carry chains : 0

    Clock Report

    ################### Begin Clock Report ######################
    Clock Nets
    Number of Clocks: 1
      Net : CLK1_c, loads : 24
    Clock Enable Nets
    Number of Clock Enables: 1
      Net : VCC_net, loads : 26
    Highest fanout non-clock nets
    Top 10 highest fanout non-clock nets:
      Net : VCC_net, loads : 26
      Net : A_c_7, loads : 1
      Net : A_c_6, loads : 1
      Net : A_c_5, loads : 1
      Net : A_c_4, loads : 1
      Net : A_c_3, loads : 1
      Net : A_c_2, loads : 1
      Net : A_c_1, loads : 1
      Net : A_c_0, loads : 1
      Net : B_c_7, loads : 1
    ################### End Clock Report ##################

    Peak Memory Usage: 350 MB

    --------------------------------------------------------------
    Total CPU Time: 0 secs
    Total REAL Time: 4 secs
    --------------------------------------------------------------