`

    #Build: Synplify Pro (R) U-2023.03LR-1, Build 098R, May 29 2023
    #install: C:\lscc\radiant\2023.1\synpbase
    #OS: Windows 10 or later
    #Hostname: DESKTOP-CQ0R02Q

    # Tue Nov 21 17:56:13 2023

    #Implementation: impl_1

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys HDL Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys VHDL Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N: :  | Running in 64-bit mode
    @N: : Reset_Sync.vhd(6) | Top entity is set to Top.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB07_Logic_Opt\LAB07\source\impl_1\Reset_Sync.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\cae_library\synthesis\vhdl\lfcpnx.vhd'.
    VHDL syntax check successful!
    File D:\02_LSCC\09_GSR\Final\LAB07_Logic_Opt\LAB07\source\impl_1\Reset_Sync.vhd changed - recompiling

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)

    Process completed successfully.
    # Tue Nov 21 17:56:14 2023

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys Verilog Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N: :  | Running in 64-bit mode
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\lfcpnx.v" (library work)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
    @N:CG334 : lscc_add_sub.v(313) | Read directive translate_off.
    @N:CG333 : lscc_add_sub.v(333) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
    @N:CG334 : pmi_complex_mult.v(92) | Read directive translate_off.
    @N:CG333 : pmi_complex_mult.v(101) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
    @N:CG334 : lscc_cntr.v(129) | Read directive translate_off.
    @N:CG333 : lscc_cntr.v(143) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
    @N:CG334 : pmi_distributed_shift_reg.v(126) | Read directive translate_off.
    @N:CG333 : pmi_distributed_shift_reg.v(135) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v" (library work)
    @N:CG334 : lscc_fifo.v(3267) | Read directive translate_off.
    @N:CG333 : lscc_fifo.v(3274) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v" (library work)
    @N:CG334 : lscc_fifo_dc.v(4907) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4911) | Read directive translate_on.
    @N:CG334 : lscc_fifo_dc.v(4942) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4946) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
    @N:CG334 : pmi_mac.v(94) | Read directive translate_off.
    @N:CG333 : pmi_mac.v(109) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
    @N:CG334 : lscc_mult_add_sub_sum.v(210) | Read directive translate_off.
    @N:CG333 : lscc_mult_add_sub_sum.v(227) | Read directive translate_on.
    @N:CG334 : pmi_multaddsubsum.v(84) | Read directive translate_off.
    @N:CG333 : pmi_multaddsubsum.v(93) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
    @N:CG334 : pmi_multaddsub.v(91) | Read directive translate_off.
    @N:CG333 : pmi_multaddsub.v(100) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
    @N:CG334 : pmi_mult.v(87) | Read directive translate_off.
    @N:CG333 : pmi_mult.v(96) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v" (library work)
    @N:CG334 : lscc_ram_dp.v(1059) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1063) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp.v(1094) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1098) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v" (library work)
    @N:CG334 : pmi_ram_dp_be.v(146) | Read directive translate_off.
    @N:CG333 : pmi_ram_dp_be.v(155) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work)
    @N:CG334 : lscc_ram_dp_true.v(1876) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1881) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1912) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1916) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1949) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1954) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1984) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1988) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2504) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2509) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2540) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2544) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2577) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2582) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2613) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2617) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3104) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3109) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3140) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3144) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3177) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3182) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3213) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3217) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v" (library work)
    @N:CG334 : lscc_ram_dq.v(1481) | Read directive translate_off.
    @N:CG333 : lscc_ram_dq.v(1487) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v" (library work)
    @N:CG334 : pmi_ram_dq_be.v(87) | Read directive translate_off.
    @N:CG333 : pmi_ram_dq_be.v(95) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v" (library work)
    @N:CG334 : lscc_rom.v(969) | Read directive translate_off.
    @N:CG333 : lscc_rom.v(975) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
    Verilog syntax check successful!

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB)

    Process completed successfully.
    # Tue Nov 21 17:56:14 2023

    ###########################################################]
    ###########################################################[
    @N: : Reset_Sync.vhd(6) | Top entity is set to Top.
    File D:\02_LSCC\09_GSR\Final\LAB07_Logic_Opt\LAB07\source\impl_1\Reset_Sync.vhd changed - recompiling
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB07_Logic_Opt\LAB07\source\impl_1\Reset_Sync.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\cae_library\synthesis\vhdl\lfcpnx.vhd'.
    VHDL syntax check successful!
    File D:\02_LSCC\09_GSR\Final\LAB07_Logic_Opt\LAB07\source\impl_1\Reset_Sync.vhd changed - recompiling
    @N:CD630 : Reset_Sync.vhd(6) | Synthesizing work.top.rtl.
    @W:CD434 : Reset_Sync.vhd(20) | Signal rst in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
    Post processing for work.top.rtl
    Running optimization stage 1 on Top .......
    Finished optimization stage 1 on Top (CPU Time 0h:00m:00s, Memory Used current: 103MB peak: 104MB)
    Running optimization stage 2 on Top .......
    @N:CL159 : Reset_Sync.vhd(8) | Input RST is unused.
    Finished optimization stage 2 on Top (CPU Time 0h:00m:00s, Memory Used current: 103MB peak: 104MB)

    For a summary of runtime per design unit, please see file:
    ==========================================================
    Linked File:  layer0.duruntime

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 104MB)

    Process completed successfully.
    # Tue Nov 21 17:56:15 2023

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Tue Nov 21 17:56:15 2023

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  LAB07_impl_1_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 24MB)

    Process took 0h:00m:02s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Tue Nov 21 17:56:16 2023

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N: :  | Running in 64-bit mode
    File D:\02_LSCC\09_GSR\Final\LAB07_Logic_Opt\LAB07\impl_1\synwork\LAB07_impl_1_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Tue Nov 21 17:56:17 2023

    ###########################################################]

`
`

    Premap Report

`
`

    # Tue Nov 21 17:56:17 2023

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys Lattice Technology Pre-mapping, Version map202303lat, Build 070R, Built Jun  8 2023 11:14:23, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 136MB)

    @A:MF827 :  | No constraint file specified.
    Linked File:  LAB07_impl_1_scck.rpt
    See clock summary report "D:\02_LSCC\09_GSR\Final\LAB07_Logic_Opt\LAB07\impl_1\LAB07_impl_1_scck.rpt"
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 136MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 136MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

    NConnInternalConnection caching is on

    Starting HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)

    Finished HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)

    Started DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)

    Finished DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 195MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 196MB)

    @N:FX1184 :  | Applying syn_allowed_resources blockrams=208 on top level netlist Top

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 196MB)

    Clock Summary
    ******************

              Start        Requested     Requested     Clock        Clock          Clock
    Level     Clock        Frequency     Period        Type         Group          Load
    ------------------------------------------------------------------------------------
    0 -       Top|CLK1     200.0 MHz     5.000         inferred     (multiple)     3
    ====================================================================================

    Clock Load Summary
    ***********************

                 Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin
    Clock        Load      Pin            Seq Example     Seq Example       Comb Example
    -------------------------------------------------------------------------------------
    Top|CLK1     3         CLK1(port)     Ai.C            -                 -
    =====================================================================================

    @W:MT530 : reset_sync.vhd(26) | Found inferred clock Top|CLK1 which controls 3 sequential elements including D. This clock has no specified timing constraint which may adversely impact design performance.

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    1 non-gated/non-generated clock tree(s) driving 3 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    ClockId_0_0       CLK1                port                   3          D
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    Summary of user generated gated clocks:
    0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)

    Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 198MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Nov 21 17:56:19 2023

    ###########################################################]

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    Map & Optimize Report

`
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    # Tue Nov 21 17:56:19 2023

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : impl_1
    Synopsys Lattice Technology Mapper, Version map202303lat, Build 070R, Built Jun  8 2023 11:14:23, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 136MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 192MB)

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)

    Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 197MB)

    Available hyper_sources - for debug and ip models
    	None Found

    NConnInternalConnection caching is on

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB)

    Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB)

    Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 198MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		     3.87ns		   1 /         3

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 198MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 199MB)

    Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 199MB)

    Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 199MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 199MB)

    Writing Analyst data base D:\02_LSCC\09_GSR\Final\LAB07_Logic_Opt\LAB07\impl_1\synwork\LAB07_impl_1_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 199MB peak: 199MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 200MB peak: 200MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 200MB peak: 201MB)

    Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 200MB peak: 201MB)

    Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 200MB peak: 201MB)

    @W:MT420 :  | Found inferred clock Top|CLK1 with period 5.00ns. Please declare a user-defined clock on port CLK1.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Tue Nov 21 17:56:21 2023
    #

    Top view:               Top
    Requested Frequency:    200.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: 3.693

                       Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group
    ------------------------------------------------------------------------------------------------------------
    Top|CLK1           200.0 MHz     765.1 MHz     5.000         1.307         3.693     inferred     (multiple)
    ============================================================================================================

    Clock Relationships
    *******************

    Clocks              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ----------------------------------------------------------------------------------------------------------
    Starting  Ending    |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    ----------------------------------------------------------------------------------------------------------
    Top|CLK1  Top|CLK1  |  5.000       3.693  |  No paths    -      |  No paths    -      |  No paths    -
    ==========================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: Top|CLK1
    ====================================

    Starting Points with Worst Slack
    ********************************

                 Starting                                   Arrival
    Instance     Reference     Type         Pin     Net     Time        Slack
                 Clock
    -------------------------------------------------------------------------
    Ai_0io       Top|CLK1      IFD1P3IX     Q       Ai      0.753       3.693
    Bi_0io       Top|CLK1      IFD1P3IX     Q       Bi      0.753       3.693
    =========================================================================

    Ending Points with Worst Slack
    ******************************

                 Starting                                   Required
    Instance     Reference     Type         Pin     Net     Time         Slack
                 Clock
    --------------------------------------------------------------------------
    D_0io        Top|CLK1      OFD1P3IX     D       D_1     4.789        3.693
    ==========================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.000
        - Setup time:                            0.211
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.789

        - Propagation time:                      1.096
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     3.693

        Number of logic level(s):                1
        Starting point:                          Ai_0io / Q
        Ending point:                            D_0io / D
        The start point is clocked by            Top|CLK1 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
        The end   point is clocked by            Top|CLK1 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

    Instance / Net                  Pin      Pin               Arrival     No. of
    Name               Type         Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------
    Ai_0io             IFD1P3IX     Q        Out     0.753     0.753 r     -
    Ai                 Net          -        -       -         -           1
    D_1                LUT4         A        In      0.000     0.753 r     -
    D_1                LUT4         Z        Out     0.343     1.096 r     -
    D_1                Net          -        -       -         -           1
    D_0io              OFD1P3IX     D        In      0.000     1.096 r     -
    =================================================================================

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 201MB)

    Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 201MB)

    ---------------------------------------
    Resource Usage Report
    Part: lfcpnx_100-9

    Register bits: 3 of 79872 (0%)
    PIC Latch:       0
    I/O cells:       4

    Details:
    GSR:            1
    IB:             3
    IFD1P3IX:       2
    LUT4:           1
    OB:             1
    OFD1P3IX:       1
    VHI:            1
    VLO:            1

    Resource Usage inside macros:
    Registers: 0
    LUTs: 0
    EBRs: 0
    LRAMs: 0
    DSPs: 0
    Distributed RAMs: 0
    Carry Chains: 0
    Blackboxes: 0

    Mapping Summary:
    Total number of registers: 3 + 0 = 3 of 79872 (0.00%)
    Total number of LUTs: 1 + 0 = 1
    Total number of EBRs: 0 + 0 = 0 of 208 (0.00%)
    Total number of LRAMs: 0 + 0 = 0 of 7 (0.00%)
    Total number of DSPs: 0 + 0 = 0 of 156 (0.00%)
    Total number of Distributed RAMs: 0 + 0 = 0
    Total number of Carry Chains: 0 + 0 = 0
    Total number of BlackBoxes: 3 + 0 = 3
    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 62MB peak: 201MB)

    Process took 0h:00m:02s realtime, 0h:00m:01s cputime
    # Tue Nov 21 17:56:22 2023

    ###########################################################]

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