                             Lattice Mapping Report File
    Design:  Top
    Family:  LFCPNX
    Device:  LFCPNX-100
    Package: LFG672
    Performance Grade:  9_High-Performance_1.0V

    Mapper:    version Radiant Software (64-bit) 2023.1.1.200.1
    Mapped on: Fri Dec  1 10:23:37 2023

    Design Information

    Command line:   map -i LAB04_impl1_syn.udb -pdc
         D:/02_LSCC/09_GSR/Final/LAB04_GSR_LSR/source/impl1/Myconstraints.pdc -o
         LAB04_impl1_map.udb -mp LAB04_impl1.mrp -hierrpt -gui

    Design Summary
       Number of registers:          38 out of 80769 (<1%)
          Number of SLICE         registers:   36 out of 79872 (<1%)
          Number of PIO Input     registers:    0 out of   299 (0%)
          Number of PIO Output    registers:    2 out of   299 (1%)
          Number of PIO Tri-State registers:    0 out of   299 (0%)
       Number of LUT4s:              40 out of 79872 (<1%)
          Number used as logic LUT4s:                          4
          Number used as distributed RAM:                      0 (6 per 16X4 RAM)
          Number used as ripple logic:                        36 (2 per CCU2)
       Number of PIOs used/reserved:   13 out of   299 (4%)
          Number of PIOs reserved:      7 (per sysConfig and/or prohibit constraint)
          Number of PIOs used:          6
            Number of PIOs used for single ended IO:         6
            Number of PIO pairs used for differential IO:    0
            Number allocated to regular speed PIOs:     6 out of  167 (4%)
            Number allocated to high speed PIOs:        0 out of  132 (0%)
       Number of Dedicated IO used for ADC/PCS/PCIE:    0 out of   60 (0%)
       Number of IDDR/ODDR/TDDR functions used:      0 out of   730 (0%)
       Number of IOs using at least one DDR function: 0 (0 differential)
       Number of Block RAMs:          0 out of 208 (0%)
       Number of Large RAMs:          0 out of 7 (0%)
       Number of Logical DSP Functions:
          Number of Pre-Adders (9+9):    0 out of 312 (0%)
          Number of Multipliers (18x18): 0 out of 156 (0%)
             Number of 9X9:        0 (1 18x18 = 2   9x9)
             Number of 18x18:      0 (1 18x18 = 1 18x18)
             Number of 18x36:      0 (2 18x18 = 1 18x36)
             Number of 36x36:      0 (4 18x18 = 1 36x36)
          Number of 54-bit Accumulators: 0 out of 78 (0%)
          Number of 18-bit Registers:    0 out of 312 (0%)
       Number of Physical DSP Components:
          Number of PREADD9:             0 out of 312 (0%)
          Number of MULT9:               0 out of 312 (0%)
          Number of MULT18:              0 out of 156 (0%)
          Number of MULT18X36:           0 out of 78 (0%)
          Number of MULT36:              0 out of 39 (0%)
          Number of ACC54:               0 out of 78 (0%)
          Number of REG18:               0 out of 312 (0%)
       Number of ALUREGs:             0 out of 1 (0%)
       Number of PLLs:                0 out of 4 (0%)
       Number of DDRDLLs:             0 out of 2 (0%)

       Number of DLLDELs:             0 out of 10 (0%)
       Number of DQSs:                0 out of 11 (0%)
       Number of DCSs:                0 out of 2 (0%)
       Number of DCCs:                0 out of 62 (0%)
       Number of PCLKDIVs:            0 out of 2 (0%)
       Number of ECLKDIVs:            0 out of 12 (0%)
       Number of ECLKSYNCs:           0 out of 12 (0%)
       Number of ADC Blocks:          0 out of 1 (0%)
       Number of SGMIICDRs:           0 out of 2 (0%)
       Number of PMUs:                0 out of 1 (0%)
       Number of BNKREF18s:           0 out of 3 (0%)
       Number of BNKREF33s:           0 out of 5 (0%)
       Number of I2CFIFOs:            0 out of 1 (0%)
       Number of Oscillators:         0 out of 1 (0%)
       Number of GSR:                 1 out of 1 (100%)
       Number of Cryptographic Block: 0 out of 1 (0%)
       Number of Config IP:           0 out of 1 (0%)
                     TSALL:           0 out of 1 (0%)
       Number of JTAG:                0 out of 1 (0%)
       Number of SED:                 0 out of 1 (0%)
       Number of PCSs:                0 out of 2 (0%)
       Number of PCIE Link Layers:    0 out of 1 (0%)
       Number of Clocks:  2
          Net CLK1_c: 12 loads, 12 rising, 0 falling (Driver: Port CLK1)
          Net clk2_c: 12 loads, 12 rising, 0 falling (Driver: Port clk2)
       Number of Clock Enables:  0
       Number of LSRs:  3
          Pin reset: 4 loads, 4 SLICEs (Net: reset_c)
          Net RST001.rst1: 10 loads, 9 SLICEs
          Net RST002.rst2: 10 loads, 9 SLICEs
       Top 10 highest fanout non-clock nets:
          Net RST001.rst1: 10 loads
          Net RST002.rst2: 10 loads
          Net reset_c: 4 loads
          Net CNT1[0]: 3 loads
          Net CNT2[0]: 3 loads
          Net CNT01.un3_couti[15]: 2 loads
          Net CNT01.un3_couti_cry_12: 2 loads
          Net CNT01.un3_couti_cry_14: 2 loads
          Net CNT1[15]: 2 loads
          Net CNT2[15]: 2 loads

       Number of warnings:  0
       Number of errors:    0

    Design Errors/Warnings

       No errors or warnings present.

    IO (PIO) Attributes

    +---------------------+-----------+-----------+-------+-------+-----------+

    | IO Name             | Direction | Levelmode |  IO   |  IO   | Special   |
    |                     |           |  IO_TYPE  |  REG  |  DDR  | IO Buffer |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED2                | OUTPUT    |           | O     |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | LED1                | OUTPUT    |           | O     |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | clk2                | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | CLK1                | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | G_reset             | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | reset               | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+

    Removed logic

    Block VCC_cZ was optimized away.
    Block GND_cZ was optimized away.
    Block RST002/Rst_Sync_RNIELAF was optimized away.
    Block RST001/Rst_Sync_RNIDC6A was optimized away.
    Block reset_pad_RNIN9FD was optimized away.
    Block VCC_cZ was optimized away.

    GSR Usage
    ---------

    GSR Component:
       The Global Set Reset (GSR) resource has been used to implement a global reset
            of the design. The reset signal used for GSR control is 'G_reset_c'.

    GSR Property:
       The design components with GSR property set to ENABLED will respond to global
            set reset while the components with GSR property set to DISABLED will
            not.

    Components with synchronous local reset also reset by asynchronous GSR
    ----------------------------------------------------------------------

    These components have the GSR property set to ENABLED and the local reset is
         synchronous. The components will respond to the synchronous local reset and
         to the unrelated asynchronous reset signal 'G_reset_c' via the GSR
         component.

    Type and number of components of the type:
       Register = 34

    Type and instance name of component:
       Register : CNT01.Couti[0].ff_inst
       Register : CNT01.Couti_reg[1].ff_inst
       Register : CNT01.Couti_reg[2].ff_inst
       Register : CNT01.Couti_reg[3].ff_inst
       Register : CNT01.Couti_reg[4].ff_inst
       Register : CNT01.Couti_reg[5].ff_inst
       Register : CNT01.Couti_reg[6].ff_inst
       Register : CNT01.Couti_reg[7].ff_inst
       Register : CNT01.Couti_reg[8].ff_inst
       Register : CNT01.Couti_reg[9].ff_inst
       Register : CNT01.Couti_reg[10].ff_inst
       Register : CNT01.Couti_reg[11].ff_inst

       Register : CNT01.Couti_reg[12].ff_inst
       Register : CNT01.Couti_reg[13].ff_inst
       Register : CNT01.Couti_reg[14].ff_inst
       Register : CNT01.Couti[15].ff_inst
       Register : CNT02.Couti[0].ff_inst
       Register : CNT02.Couti_reg[1].ff_inst
       Register : CNT02.Couti_reg[2].ff_inst
       Register : CNT02.Couti_reg[3].ff_inst
       Register : CNT02.Couti_reg[4].ff_inst
       Register : CNT02.Couti_reg[5].ff_inst
       Register : CNT02.Couti_reg[6].ff_inst
       Register : CNT02.Couti_reg[7].ff_inst
       Register : CNT02.Couti_reg[8].ff_inst
       Register : CNT02.Couti_reg[9].ff_inst
       Register : CNT02.Couti_reg[10].ff_inst
       Register : CNT02.Couti_reg[11].ff_inst
       Register : CNT02.Couti_reg[12].ff_inst
       Register : CNT02.Couti_reg[13].ff_inst
       Register : CNT02.Couti_reg[14].ff_inst
       Register : CNT02.Couti[15].ff_inst
       Register : LED2_0io.PIC_inst
       Register : LED1_0io.PIC_inst

    Constraint Summary
    ------------------

       Total number of constraints: 9
       Total number of constraints dropped: 0

    Run Time and Memory Usage
    -------------------------

       Total CPU Time: 0 secs
       Total REAL Time: 5 secs
       Peak Memory Usage: 574 MB

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