`

    #Build: Synplify Pro (R) U-2023.03LR-1, Build 098R, May 29 2023
    #install: C:\lscc\radiant\2023.1\synpbase
    #OS: Windows 10 or later
    #Hostname: DESKTOP-CQ0R02Q

    # Wed Nov 29 09:20:14 2023

    #Implementation: imp1

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : imp1
    Synopsys HDL Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N: :  | Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : imp1
    Synopsys VHDL Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N: :  | Running in 64-bit mode
    @N: : top.vhd(6) | Top entity is set to Top.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\reveal_coretop.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\mysettings.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\ce_sync_uniq_0.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_0.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_1.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_2.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_3.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\top.vhd'.
    VHDL syntax check successful!
    File D:\02_LSCC\09_GSR\Final\LAB04_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\reveal_coretop.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\mysettings.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\ce_sync_uniq_0.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_0.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_1.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_2.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_3.vhd changed - recompiling
    File D:\02_LSCC\09_GSR\Final\LAB04_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\top.vhd changed - recompiling

    At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 89MB)

    Process completed successfully.
    # Wed Nov 29 09:20:14 2023

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : imp1
    Synopsys Verilog Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N: :  | Running in 64-bit mode
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\lfcpnx.v" (library work)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
    @N:CG334 : lscc_add_sub.v(313) | Read directive translate_off.
    @N:CG333 : lscc_add_sub.v(333) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
    @N:CG334 : pmi_complex_mult.v(92) | Read directive translate_off.
    @N:CG333 : pmi_complex_mult.v(101) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
    @N:CG334 : lscc_cntr.v(129) | Read directive translate_off.
    @N:CG333 : lscc_cntr.v(143) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
    @N:CG334 : pmi_distributed_shift_reg.v(126) | Read directive translate_off.
    @N:CG333 : pmi_distributed_shift_reg.v(135) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v" (library work)
    @N:CG334 : lscc_fifo.v(3267) | Read directive translate_off.
    @N:CG333 : lscc_fifo.v(3274) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v" (library work)
    @N:CG334 : lscc_fifo_dc.v(4907) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4911) | Read directive translate_on.
    @N:CG334 : lscc_fifo_dc.v(4942) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4946) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
    @N:CG334 : pmi_mac.v(94) | Read directive translate_off.
    @N:CG333 : pmi_mac.v(109) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
    @N:CG334 : lscc_mult_add_sub_sum.v(210) | Read directive translate_off.
    @N:CG333 : lscc_mult_add_sub_sum.v(227) | Read directive translate_on.
    @N:CG334 : pmi_multaddsubsum.v(84) | Read directive translate_off.
    @N:CG333 : pmi_multaddsubsum.v(93) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
    @N:CG334 : pmi_multaddsub.v(91) | Read directive translate_off.
    @N:CG333 : pmi_multaddsub.v(100) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
    @N:CG334 : pmi_mult.v(87) | Read directive translate_off.
    @N:CG333 : pmi_mult.v(96) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v" (library work)
    @N:CG334 : lscc_ram_dp.v(1059) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1063) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp.v(1094) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1098) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v" (library work)
    @N:CG334 : pmi_ram_dp_be.v(146) | Read directive translate_off.
    @N:CG333 : pmi_ram_dp_be.v(155) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work)
    @N:CG334 : lscc_ram_dp_true.v(1876) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1881) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1912) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1916) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1949) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1954) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1984) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1988) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2504) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2509) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2540) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2544) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2577) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2582) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2613) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2617) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3104) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3109) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3140) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3144) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3177) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3182) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3213) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3217) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v" (library work)
    @N:CG334 : lscc_ram_dq.v(1481) | Read directive translate_off.
    @N:CG333 : lscc_ram_dq.v(1487) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v" (library work)
    @N:CG334 : pmi_ram_dq_be.v(87) | Read directive translate_off.
    @N:CG333 : pmi_ram_dq_be.v(95) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v" (library work)
    @N:CG334 : lscc_rom.v(969) | Read directive translate_off.
    @N:CG333 : lscc_rom.v(975) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
    @I::"C:\lscc\radiant\2023.1\data\reveal\src\ertl\ertl.v" (library work)
    @W:CG1337 : ertl.v(242) | Net jupdate_int is not declared.
    @W:CG1337 : ertl.v(243) | Net jupdate_early is not declared.
    @I::"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v" (library work)
    @W:CG1337 : JTAG_SOFT.v(70) | Net JTDIb is not declared.
    @W:CG1337 : JTAG_SOFT.v(71) | Net JCE1b is not declared.
    @W:CG1337 : JTAG_SOFT.v(72) | Net JCE2b is not declared.
    @W:CG1337 : JTAG_SOFT.v(73) | Net JRSTNb is not declared.
    @W:CG1337 : JTAG_SOFT.v(74) | Net JSHIFTb is not declared.
    @W:CG1337 : JTAG_SOFT.v(75) | Net JUPDATEb is not declared.
    @W:CG1337 : JTAG_SOFT.v(76) | Net JRTI1b is not declared.
    @W:CG1337 : JTAG_SOFT.v(77) | Net JRTI2b is not declared.
    @W:CG1337 : JTAG_SOFT.v(78) | Net JTCKb is not declared.
    @W:CS141 : JTAG_SOFT.v(802) | Unrecognized synthesis directive state. Verify the correct directive name.
    @I::"D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\top_la0_trig_gen.v" (library work)
    @I::"D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\top_la0_gen.v" (library work)
    Verilog syntax check successful!

    At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 133MB)

    Process completed successfully.
    # Wed Nov 29 09:20:15 2023

    ###########################################################]
    ###########################################################[
    @N: : top.vhd(6) | Top entity is set to Top.
    Options changed - recompiling
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\reveal_coretop.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\mysettings.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\ce_sync_uniq_0.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_0.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_1.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_2.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\cnt_uniq_3.vhd'.
    @N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\top.vhd'.
    VHDL syntax check successful!
    Options changed - recompiling
    @N:CD630 : top.vhd(6) | Synthesizing work.top.behave.
    Running optimization stage 1 on OSCA .......
    Finished optimization stage 1 on OSCA (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
    @W:CD638 : top.vhd(237) | Signal reveal_in is undriven. Either assign the signal a value or remove the signal declaration.
    @W:CD638 : top.vhd(238) | Signal reveal_out is undriven. Either assign the signal a value or remove the signal declaration.
    @N:CD630 : reveal_coretop.vhd(4) | Synthesizing work.reveal_coretop.one.
    @W:CD638 : reveal_coretop.vhd(27) | Signal trigger_out is undriven. Either assign the signal a value or remove the signal declaration.
    Running optimization stage 1 on top_la0 .......
    Finished optimization stage 1 on top_la0 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Post processing for work.reveal_coretop.one
    Running optimization stage 1 on reveal_coretop .......
    Finished optimization stage 1 on reveal_coretop (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    @N:CD630 : cnt_uniq_3.vhd(5) | Synthesizing work.cnt_uniq_3.rtl.
    Post processing for work.cnt_uniq_3.rtl
    Running optimization stage 1 on CNT_uniq_3 .......
    Finished optimization stage 1 on CNT_uniq_3 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    @N:CD630 : cnt_uniq_2.vhd(5) | Synthesizing work.cnt_uniq_2.rtl.
    Post processing for work.cnt_uniq_2.rtl
    Running optimization stage 1 on CNT_uniq_2 .......
    Finished optimization stage 1 on CNT_uniq_2 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    @N:CD630 : cnt_uniq_1.vhd(5) | Synthesizing work.cnt_uniq_1.rtl.
    Post processing for work.cnt_uniq_1.rtl
    Running optimization stage 1 on CNT_uniq_1 .......
    Finished optimization stage 1 on CNT_uniq_1 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    @N:CD630 : cnt_uniq_0.vhd(5) | Synthesizing work.cnt_uniq_0.rtl.
    Post processing for work.cnt_uniq_0.rtl
    Running optimization stage 1 on CNT_uniq_0 .......
    Finished optimization stage 1 on CNT_uniq_0 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    @N:CD630 : ce_sync_uniq_0.vhd(5) | Synthesizing work.ce_sync_uniq_0.rtl.
    Running optimization stage 1 on DCC .......
    Finished optimization stage 1 on DCC (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Post processing for work.ce_sync_uniq_0.rtl
    Running optimization stage 1 on CE_Sync_uniq_0 .......
    Finished optimization stage 1 on CE_Sync_uniq_0 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Post processing for work.top.behave
    Running optimization stage 1 on Top .......
    Finished optimization stage 1 on Top (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Running optimization stage 2 on DCC .......
    Finished optimization stage 2 on DCC (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Running optimization stage 2 on CE_Sync_uniq_0 .......
    Finished optimization stage 2 on CE_Sync_uniq_0 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Running optimization stage 2 on CNT_uniq_0_work_top_behave_0layer0 .......
    Finished optimization stage 2 on CNT_uniq_0_work_top_behave_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Running optimization stage 2 on CNT_uniq_1_work_top_behave_0layer0 .......
    Finished optimization stage 2 on CNT_uniq_1_work_top_behave_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Running optimization stage 2 on CNT_uniq_2_work_top_behave_0layer0 .......
    Finished optimization stage 2 on CNT_uniq_2_work_top_behave_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Running optimization stage 2 on CNT_uniq_3_work_top_behave_0layer0 .......
    Finished optimization stage 2 on CNT_uniq_3_work_top_behave_0layer0 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Running optimization stage 2 on top_la0 .......
    Finished optimization stage 2 on top_la0 (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Running optimization stage 2 on reveal_coretop .......
    Finished optimization stage 2 on reveal_coretop (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Running optimization stage 2 on OSCA .......
    Finished optimization stage 2 on OSCA (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
    Running optimization stage 2 on Top .......
    Finished optimization stage 2 on Top (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)

    For a summary of runtime per design unit, please see file:
    ==========================================================
    Linked File:  layer0.duruntime

    At c_vhdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 95MB)

    Process completed successfully.
    # Wed Nov 29 09:20:18 2023

    ###########################################################]
    ###########################################################[
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\lfcpnx.v" (library work)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
    @N:CG334 : lscc_add_sub.v(313) | Read directive translate_off.
    @N:CG333 : lscc_add_sub.v(333) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
    @N:CG334 : pmi_complex_mult.v(92) | Read directive translate_off.
    @N:CG333 : pmi_complex_mult.v(101) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
    @N:CG334 : lscc_cntr.v(129) | Read directive translate_off.
    @N:CG333 : lscc_cntr.v(143) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
    @N:CG334 : pmi_distributed_shift_reg.v(126) | Read directive translate_off.
    @N:CG333 : pmi_distributed_shift_reg.v(135) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v" (library work)
    @N:CG334 : lscc_fifo.v(3267) | Read directive translate_off.
    @N:CG333 : lscc_fifo.v(3274) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v" (library work)
    @N:CG334 : lscc_fifo_dc.v(4907) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4911) | Read directive translate_on.
    @N:CG334 : lscc_fifo_dc.v(4942) | Read directive translate_off.
    @N:CG333 : lscc_fifo_dc.v(4946) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
    @N:CG334 : pmi_mac.v(94) | Read directive translate_off.
    @N:CG333 : pmi_mac.v(109) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
    @N:CG334 : lscc_mult_add_sub_sum.v(210) | Read directive translate_off.
    @N:CG333 : lscc_mult_add_sub_sum.v(227) | Read directive translate_on.
    @N:CG334 : pmi_multaddsubsum.v(84) | Read directive translate_off.
    @N:CG333 : pmi_multaddsubsum.v(93) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
    @N:CG334 : pmi_multaddsub.v(91) | Read directive translate_off.
    @N:CG333 : pmi_multaddsub.v(100) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
    @N:CG334 : pmi_mult.v(87) | Read directive translate_off.
    @N:CG333 : pmi_mult.v(96) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v" (library work)
    @N:CG334 : lscc_ram_dp.v(1059) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1063) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp.v(1094) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp.v(1098) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v" (library work)
    @N:CG334 : pmi_ram_dp_be.v(146) | Read directive translate_off.
    @N:CG333 : pmi_ram_dp_be.v(155) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work)
    @N:CG334 : lscc_ram_dp_true.v(1876) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1881) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1912) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1916) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1949) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1954) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(1984) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(1988) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2504) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2509) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2540) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2544) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2577) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2582) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(2613) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(2617) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3104) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3109) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3140) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3144) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3177) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3182) | Read directive translate_on.
    @N:CG334 : lscc_ram_dp_true.v(3213) | Read directive translate_off.
    @N:CG333 : lscc_ram_dp_true.v(3217) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v" (library work)
    @N:CG334 : lscc_ram_dq.v(1481) | Read directive translate_off.
    @N:CG333 : lscc_ram_dq.v(1487) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v" (library work)
    @N:CG334 : pmi_ram_dq_be.v(87) | Read directive translate_off.
    @N:CG333 : pmi_ram_dq_be.v(95) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v" (library work)
    @N:CG334 : lscc_rom.v(969) | Read directive translate_off.
    @N:CG333 : lscc_rom.v(975) | Read directive translate_on.
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v" (library work)
    @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
    @I::"C:\lscc\radiant\2023.1\data\reveal\src\ertl\ertl.v" (library work)
    @W:CG1337 : ertl.v(242) | Net jupdate_int is not declared.
    @W:CG1337 : ertl.v(243) | Net jupdate_early is not declared.
    @I::"C:\lscc\radiant\2023.1\data\reveal\src\ertl\JTAG_SOFT.v" (library work)
    @W:CG1337 : JTAG_SOFT.v(70) | Net JTDIb is not declared.
    @W:CG1337 : JTAG_SOFT.v(71) | Net JCE1b is not declared.
    @W:CG1337 : JTAG_SOFT.v(72) | Net JCE2b is not declared.
    @W:CG1337 : JTAG_SOFT.v(73) | Net JRSTNb is not declared.
    @W:CG1337 : JTAG_SOFT.v(74) | Net JSHIFTb is not declared.
    @W:CG1337 : JTAG_SOFT.v(75) | Net JUPDATEb is not declared.
    @W:CG1337 : JTAG_SOFT.v(76) | Net JRTI1b is not declared.
    @W:CG1337 : JTAG_SOFT.v(77) | Net JRTI2b is not declared.
    @W:CG1337 : JTAG_SOFT.v(78) | Net JTCKb is not declared.
    @W:CS141 : JTAG_SOFT.v(802) | Unrecognized synthesis directive state. Verify the correct directive name.
    @I::"D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\top_la0_trig_gen.v" (library work)
    @I::"D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\reveal_workspace\tmpreveal\top_la0_gen.v" (library work)
    Verilog syntax check successful!
    Running optimization stage 1 on rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s .......
    Finished optimization stage 1 on rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s (CPU Time 0h:00m:00s, Memory Used current: 138MB peak: 138MB)
    Running optimization stage 1 on rvl_decode_5s_2s .......
    Finished optimization stage 1 on rvl_decode_5s_2s (CPU Time 0h:00m:00s, Memory Used current: 138MB peak: 138MB)
    Running optimization stage 1 on rvl_tu_1s_0s_0s_0s_1s .......
    Finished optimization stage 1 on rvl_tu_1s_0s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 138MB peak: 139MB)
    Running optimization stage 1 on rvl_tu_16s_0s_0s_0s_1s .......
    Finished optimization stage 1 on rvl_tu_16s_0s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 140MB)
    Running optimization stage 1 on pmi_rtl_ram_dist_32s_5s_2s_reg_none_binary_LFCPNX .......
    Finished optimization stage 1 on pmi_rtl_ram_dist_32s_5s_2s_reg_none_binary_LFCPNX (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 140MB)
    Running optimization stage 1 on rvl_te_Z1_layer1 .......
    Finished optimization stage 1 on rvl_te_Z1_layer1 (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 140MB)
    Running optimization stage 1 on pmi_rtl_ram_dist_32s_5s_8s_reg_none_binary_LFCPNX .......
    Finished optimization stage 1 on pmi_rtl_ram_dist_32s_5s_8s_reg_none_binary_LFCPNX (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 140MB)
    Running optimization stage 1 on rvl_te_Z2_layer1 .......
    Finished optimization stage 1 on rvl_te_Z2_layer1 (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
    Running optimization stage 1 on rvl_tcnt_2s_3s_1_0s .......
    Finished optimization stage 1 on rvl_tcnt_2s_3s_1_0s (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
    @N:CG364 : top_la0_trig_gen.v(11) | Synthesizing module top_la0_trig in library work.
    Running optimization stage 1 on top_la0_trig .......
    Finished optimization stage 1 on top_la0_trig (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
    Running optimization stage 1 on pmi_rtl_ram_dp_32s_5s_65s_reg_none_binary_LFCPNX .......
    Finished optimization stage 1 on pmi_rtl_ram_dp_32s_5s_65s_reg_none_binary_LFCPNX (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
    Running optimization stage 1 on rvl_tm_Z3_layer1 .......
    Finished optimization stage 1 on rvl_tm_Z3_layer1 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 141MB)
    @N:CG364 : top_la0_gen.v(12) | Synthesizing module top_la0 in library work.
    Running optimization stage 1 on top_la0 .......
    Finished optimization stage 1 on top_la0 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 141MB)
    Running optimization stage 2 on top_la0 .......
    @N:CL159 : top_la0_gen.v(59) | Input reset_n is unused.
    @N:CL159 : top_la0_gen.v(74) | Input trigger_en is unused.
    Finished optimization stage 2 on top_la0 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 142MB)
    Running optimization stage 2 on pmi_rtl_ram_dp_32s_5s_65s_reg_none_binary_LFCPNX .......
    Finished optimization stage 2 on pmi_rtl_ram_dp_32s_5s_65s_reg_none_binary_LFCPNX (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 142MB)
    Running optimization stage 2 on rvl_tm_Z3_layer1 .......
    Finished optimization stage 2 on rvl_tm_Z3_layer1 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 144MB)
    Running optimization stage 2 on top_la0_trig .......
    Finished optimization stage 2 on top_la0_trig (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 144MB)
    Running optimization stage 2 on rvl_tcnt_2s_3s_1_0s .......
    Finished optimization stage 2 on rvl_tcnt_2s_3s_1_0s (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 144MB)
    Running optimization stage 2 on pmi_rtl_ram_dist_32s_5s_8s_reg_none_binary_LFCPNX .......
    Finished optimization stage 2 on pmi_rtl_ram_dist_32s_5s_8s_reg_none_binary_LFCPNX (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 144MB)
    Running optimization stage 2 on rvl_te_Z2_layer1 .......
    Finished optimization stage 2 on rvl_te_Z2_layer1 (CPU Time 0h:00m:00s, Memory Used current: 146MB peak: 156MB)
    Running optimization stage 2 on pmi_rtl_ram_dist_32s_5s_2s_reg_none_binary_LFCPNX .......
    Finished optimization stage 2 on pmi_rtl_ram_dist_32s_5s_2s_reg_none_binary_LFCPNX (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 156MB)
    Running optimization stage 2 on rvl_te_Z1_layer1 .......
    Extracted state machine for register next_then_shift
    State machine has 3 reachable states with original encodings of:
       00
       01
       10
    Finished optimization stage 2 on rvl_te_Z1_layer1 (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 165MB)
    Running optimization stage 2 on rvl_tu_16s_0s_0s_0s_1s .......
    Finished optimization stage 2 on rvl_tu_16s_0s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 165MB)
    Running optimization stage 2 on rvl_tu_1s_0s_0s_0s_1s .......
    Finished optimization stage 2 on rvl_tu_1s_0s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 165MB)
    Running optimization stage 2 on rvl_decode_5s_2s .......
    Finished optimization stage 2 on rvl_decode_5s_2s (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 165MB)
    Running optimization stage 2 on rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s .......
    Finished optimization stage 2 on rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s (CPU Time 0h:00m:00s, Memory Used current: 150MB peak: 165MB)

    For a summary of runtime per design unit, please see file:
    ==========================================================
    Linked File:  layer1.duruntime

    At c_ver Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 165MB)

    Process completed successfully.
    # Wed Nov 29 09:20:24 2023

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : imp1
    Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N: :  | Running in 64-bit mode
    @W:Z198 : top.vhd(249) | Unbound component OSCA of instance OSCA001
    @W:Z198 : ce_sync_uniq_0.vhd(23) | Unbound component DCC of instance DCC01

    =======================================================================================
    For a summary of linker messages for components that did not bind, please see log file:
    Linked File:  LAB04_imp1_comp.linkerlog
    =======================================================================================

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Wed Nov 29 09:20:25 2023

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    Linked File:  LAB04_imp1_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:02s; Memory used current: 24MB peak: 25MB)

    Process took 0h:00m:11s realtime, 0h:00m:02s cputime

    Process completed successfully.
    # Wed Nov 29 09:20:25 2023

    ###########################################################]

`
`

    ###########################################################[

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : imp1
    Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @

    @N: :  | Running in 64-bit mode
    File D:\02_LSCC\09_GSR\Final\LAB04_Prop_Circuit_ARST\imp1\synwork\LAB04_imp1_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 96MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Wed Nov 29 09:20:27 2023

    ###########################################################]

`
`

    # Wed Nov 29 09:20:28 2023

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : imp1
    Synopsys Lattice Technology Pre-mapping, Version map202303lat, Build 070R, Built Jun  8 2023 11:14:23, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 136MB)

    Reading constraint file: D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\source\imp1\timingsdc.sdc
    Reading constraint file: C:\lscc\radiant\2023.1\data\reveal\src\ertl\reveal_constraint.sdc
    Linked File:  LAB04_imp1_scck.rpt
    See clock summary report "D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\LAB04_imp1_scck.rpt"
    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 136MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)

    Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 151MB)

    NConnInternalConnection caching is on
    @W:BN117 : top_la0_trig_gen.v(112) | Instance decode_u of partition view:work.rvl_decode_5s_2s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(126) | Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(140) | Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(154) | Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(168) | Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(182) | Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(202) | Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(242) | Instance te_1 of partition view:work.rvl_te_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(278) | Instance tcnt_0 of partition view:work.rvl_tcnt_2s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(112) | Instance decode_u of partition view:work.rvl_decode_5s_2s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(126) | Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(140) | Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(154) | Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(168) | Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(182) | Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(202) | Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(242) | Instance te_1 of partition view:work.rvl_te_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(278) | Instance tcnt_0 of partition view:work.rvl_tcnt_2s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(112) | Instance decode_u of partition view:work.rvl_decode_5s_2s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(126) | Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(140) | Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(154) | Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(168) | Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(182) | Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(202) | Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(242) | Instance te_1 of partition view:work.rvl_te_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(278) | Instance tcnt_0 of partition view:work.rvl_tcnt_2s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(107) | Instance jtag_int_u of partition view:work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(188) | Instance tm_u of partition view:work.rvl_tm_Z3_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(107) | Instance jtag_int_u of partition view:work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(188) | Instance tm_u of partition view:work.rvl_tm_Z3_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(107) | Instance jtag_int_u of partition view:work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(188) | Instance tm_u of partition view:work.rvl_tm_Z3_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(112) | Instance decode_u of partition view:work.rvl_decode_5s_2s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(126) | Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(140) | Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(154) | Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(168) | Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(182) | Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(202) | Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(242) | Instance te_1 of partition view:work.rvl_te_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(278) | Instance tcnt_0 of partition view:work.rvl_tcnt_2s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(112) | Instance decode_u of partition view:work.rvl_decode_5s_2s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(126) | Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(140) | Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(154) | Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(168) | Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(182) | Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(202) | Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(242) | Instance te_1 of partition view:work.rvl_te_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(278) | Instance tcnt_0 of partition view:work.rvl_tcnt_2s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(112) | Instance decode_u of partition view:work.rvl_decode_5s_2s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(126) | Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(140) | Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(154) | Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(168) | Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(182) | Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(202) | Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(242) | Instance te_1 of partition view:work.rvl_te_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(278) | Instance tcnt_0 of partition view:work.rvl_tcnt_2s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(112) | Instance decode_u of partition view:work.rvl_decode_5s_2s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(126) | Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(140) | Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(154) | Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(168) | Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(182) | Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(202) | Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(242) | Instance te_1 of partition view:work.rvl_te_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(278) | Instance tcnt_0 of partition view:work.rvl_tcnt_2s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(112) | Instance decode_u of partition view:work.rvl_decode_5s_2s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(126) | Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(140) | Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(154) | Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(168) | Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(182) | Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(202) | Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(242) | Instance te_1 of partition view:work.rvl_te_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(278) | Instance tcnt_0 of partition view:work.rvl_tcnt_2s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(107) | Instance jtag_int_u of partition view:work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(188) | Instance tm_u of partition view:work.rvl_tm_Z3_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(107) | Instance jtag_int_u of partition view:work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(188) | Instance tm_u of partition view:work.rvl_tm_Z3_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(107) | Instance jtag_int_u of partition view:work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(188) | Instance tm_u of partition view:work.rvl_tm_Z3_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(107) | Instance jtag_int_u of partition view:work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(188) | Instance tm_u of partition view:work.rvl_tm_Z3_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(107) | Instance jtag_int_u of partition view:work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(188) | Instance tm_u of partition view:work.rvl_tm_Z3_layer1(verilog) has no references to its outputs; instance not removed.

    Starting HSTDM IP insertion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 201MB)

    Finished HSTDM IP insertion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 201MB)

    Started DisTri Cleanup (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 201MB)

    Finished DisTri Cleanup (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 201MB)

    @W:BN117 : top_la0_gen.v(107) | Instance jtag_int_u of partition view:work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(188) | Instance tm_u of partition view:work.rvl_tm_Z3_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(112) | Instance decode_u of partition view:work.rvl_decode_5s_2s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(126) | Instance tu_0 of partition view:work.rvl_tu_1s_0s_0s_0s_1s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(140) | Instance tu_1 of partition view:work.rvl_tu_16s_0s_0s_0s_1s_3(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(154) | Instance tu_2 of partition view:work.rvl_tu_16s_0s_0s_0s_1s_2(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(168) | Instance tu_3 of partition view:work.rvl_tu_16s_0s_0s_0s_1s_1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(182) | Instance tu_4 of partition view:work.rvl_tu_16s_0s_0s_0s_1s_0(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(202) | Instance te_0 of partition view:work.rvl_te_Z1_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(242) | Instance te_1 of partition view:work.rvl_te_Z2_layer1(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_trig_gen.v(278) | Instance tcnt_0 of partition view:work.rvl_tcnt_2s_3s_1_0s(verilog) has no references to its outputs; instance not removed.
    @W:BN117 : top_la0_gen.v(107) | Instance jtag_int_u of partition view:work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog) has no references to its outputs; instance not removed.

    Only the first 100 messages of id 'BN117' are reported. To see all messages use 'report_messages -log D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\synlog\LAB04_imp1_premap.srr -id BN117' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN117} -count unlimited' in the Tcl shell.
    Encoding state machine [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10

    Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 203MB peak: 203MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 203MB peak: 204MB)

    @N:FX1184 :  | Applying syn_allowed_resources blockrams=208 on top level netlist Top

    Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 204MB peak: 204MB)

    Some data will not be shown as it is part of encrypted module

    Clock Summary
    ******************

              Start                                  Requested     Requested     Clock        Clock                     Clock
    Level     Clock                                  Frequency     Period        Type         Group                     Load
    -------------------------------------------------------------------------------------------------------------------------
    0 -       System                                 1.0 MHz       1000.000      system       system_clkgroup           0

    0 -       rvltck                                 30.0 MHz      33.330        declared     default_clkgroup          0

    0 -       Top|CLK                                1.0 MHz       1000.000      inferred     Inferred_clkgroup_0_3     595

    0 -       Top|jtck_inferred_clock                1.0 MHz       1000.000      inferred     Inferred_clkgroup_0_2     446

    0 -       CE_Sync_uniq_0|clko_inferred_clock     1.0 MHz       1000.000      inferred     Inferred_clkgroup_0_1     68
    =========================================================================================================================

    Clock Load Summary
    ***********************

                                           Clock     Source                         Clock Pin       Non-clock Pin     Non-clock Pin
    Clock                                  Load      Pin                            Seq Example     Seq Example       Comb Example
    -------------------------------------------------------------------------------------------------------------------------------
    System                                 0         -                              -               -                 -

    rvltck                                 0         TCK(port)                      -               -                 -

    Top|CLK                                595       OSCA001.HFCLKOUT(OSCA)         CE001.CE1.C     -                 -

    Top|jtck_inferred_clock                446       jtaghub_inst.JTCK(JTAGH19)     -               -                 -

    CE_Sync_uniq_0|clko_inferred_clock     68        CE001.DCC01.CLKO(DCC)          LED1.C          -                 -
    ===============================================================================================================================

    @W:MT530 : cnt_uniq_0.vhd(51) | Found inferred clock CE_Sync_uniq_0|clko_inferred_clock which controls 68 sequential elements including CNT01.Couti[15:0]. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : ce_sync_uniq_0.vhd(30) | Found inferred clock Top|CLK which controls 595 sequential elements including CE001.CE. This clock has no specified timing constraint which may adversely impact design performance.

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    3 non-gated/non-generated clock tree(s) driving 1033 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    ============================ Non-Gated/Non-Generated Clocks =============================
    Clock Tree ID     Driving Element       Drive Element Type     Fanout     Sample Instance
    -----------------------------------------------------------------------------------------
    ClockId_0_0       jtaghub_inst.JTCK     JTAGH19                446        ENCRYPTED
    ClockId_0_1       OSCA001.HFCLKOUT      OSCA                   519        CE001.CE
    ClockId_0_3       CE001.DCC01.CLKO      DCC                    68         LED4
    =========================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    Summary of user generated gated clocks:
    0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)

    @N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.

    Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 203MB peak: 204MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 204MB peak: 204MB)

    @W:MF511 :  | Found issues with constraints. Please check constraint checker report "D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\LAB04_imp1_cck.rpt" .

    Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 205MB peak: 205MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 207MB)

    Process took 0h:00m:02s realtime, 0h:00m:01s cputime
    # Wed Nov 29 09:20:31 2023

    ###########################################################]

`
`

    Map & Optimize Report

`
`

    # Wed Nov 29 09:20:31 2023

    Copyright (C) 1994-2023 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: U-2023.03LR-1
    Install: C:\lscc\radiant\2023.1\synpbase
    OS: Windows 10 or later
    Hostname: DESKTOP-CQ0R02Q

    Implementation : imp1
    Synopsys Lattice Technology Mapper, Version map202303lat, Build 070R, Built Jun  8 2023 11:14:23, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

    @N:MF916 :  | Option synthesis_strategy=base is enabled.
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 136MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 140MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)

    Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 203MB peak: 203MB)

    @N:MO231 : cnt_uniq_3.vhd(51) | Found counter in view:work.Top(behave) instance CNT04.Couti[15:0]
    @N:MO231 : cnt_uniq_2.vhd(51) | Found counter in view:work.Top(behave) instance CNT03.Couti[15:0]
    @N:MO231 : cnt_uniq_1.vhd(51) | Found counter in view:work.Top(behave) instance CNT02.Couti[15:0]
    @N:MO231 : cnt_uniq_0.vhd(51) | Found counter in view:work.Top(behave) instance CNT01.Couti[15:0]
    @N:MF794 :  | RAM event_cntr_reg_1[2:0] required 3 registers during mapping
    @N:MF794 :  | RAM genblk1\.te_tt_dist_ram.mem[7:0] required 24 registers during mapping

    Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 208MB peak: 208MB)

    Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 213MB peak: 213MB)

    Available hyper_sources - for debug and ip models
    	None Found

    NConnInternalConnection caching is on

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 218MB peak: 218MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 219MB peak: 220MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 219MB peak: 220MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 219MB peak: 220MB)

    Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 219MB peak: 220MB)

    Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 237MB peak: 237MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		   994.65ns		1097 /      1044

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 237MB peak: 238MB)

    @N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

    Warning: Forcing use of GSR for flip-flops and
    latches that do not specify sets or resets
       LED1 (in view: work.Top(behave))
       LED2 (in view: work.Top(behave))
       LED3 (in view: work.Top(behave))
       LED4 (in view: work.Top(behave))
       [encrypted] (in view: work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog))
       [encrypted] (in view: work.rvl_jtag_int_65s_65s_0s_0s_7s_65s_65s(verilog))
       [encrypted] (in view: work.rvl_te_Z2_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z2_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z2_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z2_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z2_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z2_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z2_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z2_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_tm_Z3_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))
       [encrypted] (in view: work.rvl_te_Z1_layer1(verilog))

    Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 238MB)

    Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 239MB)

    Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 239MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:00s; Memory used current: 180MB peak: 239MB)

    Writing Analyst data base D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\imp1\synwork\LAB04_imp1_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:00s; Memory used current: 239MB peak: 239MB)

    Writing Verilog Simulation files

    Writing scf file... (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 241MB peak: 241MB)

    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF

    Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 242MB peak: 242MB)

    Finished Writing Netlists (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 242MB peak: 242MB)

    Start final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 236MB peak: 242MB)

    @W:MT246 : top.vhd(314) | Blackbox JTAGH19 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : top.vhd(249) | Blackbox OSCA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : ce_sync_uniq_0.vhd(23) | Blackbox DCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @N:MT615 :  | Found clock rvltck with period 33.33ns
    @W:MT420 :  | Found inferred clock CE_Sync_uniq_0|clko_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net CE001.CLK1.
    @W:MT420 :  | Found inferred clock Top|jtck_inferred_clock with period 1000.00ns. Please declare a user-defined clock on net jtck.
    @W:MT420 :  | Found inferred clock Top|CLK with period 1000.00ns. Please declare a user-defined clock on net CLK.

    ##### START OF TIMING REPORT #####[
    # Timing report written on Wed Nov 29 09:20:39 2023
    #

    Top view:               Top
    Requested Frequency:    1.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):    D:\02_LSCC\09_GSR\Final\LAB02_Prop_Circuit_ARST\source\imp1\timingsdc.sdc
                           C:\lscc\radiant\2023.1\data\reveal\src\ertl\reveal_constraint.sdc

    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: 994.426

                                           Requested     Estimated     Requested     Estimated                 Clock        Clock
    Starting Clock                         Frequency     Frequency     Period        Period        Slack       Type         Group
    ---------------------------------------------------------------------------------------------------------------------------------------------
    CE_Sync_uniq_0|clko_inferred_clock     1.0 MHz       396.4 MHz     1000.000      2.522         997.477     inferred     Inferred_clkgroup_0_1
    Top|CLK                                1.0 MHz       223.1 MHz     1000.000      4.482         995.518     inferred     Inferred_clkgroup_0_3
    Top|jtck_inferred_clock                1.0 MHz       179.4 MHz     1000.000      5.574         994.426     inferred     Inferred_clkgroup_0_2
    rvltck                                 30.0 MHz      NA            33.330        NA            NA          declared     default_clkgroup
    System                                 1.0 MHz       289.0 MHz     1000.000      3.461         996.539     system       system_clkgroup
    =============================================================================================================================================
    Estimated period and frequency reported as NA means no slack depends directly on the clock waveform

    Clock Relationships
    *******************

    Clocks                                                                  |    rise  to  rise     |    fall  to  fall     |    rise  to  fall     |    fall  to  rise
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                            Ending                              |  constraint  slack    |  constraint  slack    |  constraint  slack    |  constraint  slack
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                              System                              |  1000.000    996.540  |  No paths    -        |  No paths    -        |  No paths    -
    System                              Top|jtck_inferred_clock             |  No paths    -        |  No paths    -        |  1000.000    995.463  |  No paths    -
    System                              Top|CLK                             |  1000.000    996.464  |  No paths    -        |  No paths    -        |  No paths    -
    CE_Sync_uniq_0|clko_inferred_clock  CE_Sync_uniq_0|clko_inferred_clock  |  1000.000    997.478  |  No paths    -        |  No paths    -        |  No paths    -
    CE_Sync_uniq_0|clko_inferred_clock  Top|CLK                             |  Diff grp    -        |  No paths    -        |  No paths    -        |  No paths    -
    Top|jtck_inferred_clock             System                              |  No paths    -        |  No paths    -        |  No paths    -        |  1000.000    995.503
    Top|jtck_inferred_clock             Top|jtck_inferred_clock             |  No paths    -        |  1000.000    994.426  |  No paths    -        |  No paths    -
    Top|jtck_inferred_clock             Top|CLK                             |  No paths    -        |  No paths    -        |  No paths    -        |  Diff grp    -
    Top|CLK                             System                              |  1000.000    995.896  |  No paths    -        |  No paths    -        |  No paths    -
    Top|CLK                             Top|jtck_inferred_clock             |  No paths    -        |  No paths    -        |  Diff grp    -        |  No paths    -
    Top|CLK                             Top|CLK                             |  1000.000    995.518  |  No paths    -        |  No paths    -        |  No paths    -
    ======================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: CE_Sync_uniq_0|clko_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                       Starting                                                                 Arrival
    Instance           Reference                              Type        Pin     Net           Time        Slack
                       Clock
    ---------------------------------------------------------------------------------------------------------------
    CNT04.Couti[0]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     Q       CNT4_1[0]     0.863       997.477
    CNT01.Couti[0]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     Q       CNT1_1[0]     0.863       997.477
    CNT02.Couti[0]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     Q       CNT2_1[0]     0.863       997.477
    CNT03.Couti[0]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     Q       CNT3_1[0]     0.863       997.477
    CNT03.Couti[1]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     Q       CNT3_1[1]     0.838       997.562
    CNT04.Couti[1]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     Q       CNT4_1[1]     0.838       997.562
    CNT01.Couti[1]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     Q       CNT1_1[1]     0.838       997.562
    CNT02.Couti[1]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     Q       CNT2_1[1]     0.838       997.562
    CNT02.Couti[2]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     Q       CNT2_1[2]     0.838       997.562
    CNT03.Couti[2]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     Q       CNT3_1[2]     0.838       997.562
    ===============================================================================================================

    Ending Points with Worst Slack
    ******************************

                        Starting                                                                   Required
    Instance            Reference                              Type        Pin     Net             Time         Slack
                        Clock
    -------------------------------------------------------------------------------------------------------------------
    CNT02.Couti[15]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     D       Couti_s[15]     1000.144     997.477
    CNT03.Couti[15]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     D       Couti_s[15]     1000.144     997.477
    CNT01.Couti[15]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     D       Couti_s[15]     1000.144     997.477
    CNT04.Couti[15]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     D       Couti_s[15]     1000.144     997.477
    CNT03.Couti[13]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     D       Couti_s[13]     1000.144     997.537
    CNT01.Couti[13]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     D       Couti_s[13]     1000.144     997.537
    CNT04.Couti[13]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     D       Couti_s[13]     1000.144     997.537
    CNT02.Couti[13]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     D       Couti_s[13]     1000.144     997.537
    CNT01.Couti[14]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     D       Couti_s[14]     1000.144     997.537
    CNT02.Couti[14]     CE_Sync_uniq_0|clko_inferred_clock     FD1P3DX     D       Couti_s[14]     1000.144     997.537
    ===================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            -0.144
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         1000.144

        - Propagation time:                      2.667
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 997.477

        Number of logic level(s):                9
        Starting point:                          CNT04.Couti[0] / Q
        Ending point:                            CNT04.Couti[15] / D
        The start point is clocked by            CE_Sync_uniq_0|clko_inferred_clock [rising] (rise=0.000 fall=500.000 period=1000.000) on pin CK
        The end   point is clocked by            CE_Sync_uniq_0|clko_inferred_clock [rising] (rise=0.000 fall=500.000 period=1000.000) on pin CK

    Instance / Net                        Pin      Pin               Arrival     No. of
    Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------
    CNT04.Couti[0]            FD1P3DX     Q        Out     0.863     0.863 r     -
    CNT4_1[0]                 Net         -        -       -         -           4
    CNT04.Couti_cry_0[0]      CCU2        A1       In      0.000     0.863 r     -
    CNT04.Couti_cry_0[0]      CCU2        COUT     Out     0.784     1.647 r     -
    Couti_cry[0]              Net         -        -       -         -           1
    CNT04.Couti_cry_0[1]      CCU2        CIN      In      0.000     1.647 r     -
    CNT04.Couti_cry_0[1]      CCU2        COUT     Out     0.059     1.706 r     -
    Couti_cry[2]              Net         -        -       -         -           1
    CNT04.Couti_cry_0[3]      CCU2        CIN      In      0.000     1.706 r     -
    CNT04.Couti_cry_0[3]      CCU2        COUT     Out     0.059     1.765 r     -
    Couti_cry[4]              Net         -        -       -         -           1
    CNT04.Couti_cry_0[5]      CCU2        CIN      In      0.000     1.765 r     -
    CNT04.Couti_cry_0[5]      CCU2        COUT     Out     0.059     1.824 r     -
    Couti_cry[6]              Net         -        -       -         -           1
    CNT04.Couti_cry_0[7]      CCU2        CIN      In      0.000     1.824 r     -
    CNT04.Couti_cry_0[7]      CCU2        COUT     Out     0.059     1.883 r     -
    Couti_cry[8]              Net         -        -       -         -           1
    CNT04.Couti_cry_0[9]      CCU2        CIN      In      0.000     1.883 r     -
    CNT04.Couti_cry_0[9]      CCU2        COUT     Out     0.059     1.942 r     -
    Couti_cry[10]             Net         -        -       -         -           1
    CNT04.Couti_cry_0[11]     CCU2        CIN      In      0.000     1.942 r     -
    CNT04.Couti_cry_0[11]     CCU2        COUT     Out     0.059     2.001 r     -
    Couti_cry[12]             Net         -        -       -         -           1
    CNT04.Couti_cry_0[13]     CCU2        CIN      In      0.000     2.001 r     -
    CNT04.Couti_cry_0[13]     CCU2        COUT     Out     0.059     2.060 r     -
    Couti_cry[14]             Net         -        -       -         -           1
    CNT04.Couti_s_0[15]       CCU2        CIN      In      0.000     2.060 r     -
    CNT04.Couti_s_0[15]       CCU2        S0       Out     0.607     2.667 r     -
    Couti_s[15]               Net         -        -       -         -           1
    CNT04.Couti[15]           FD1P3DX     D        In      0.000     2.667 r     -
    =======================================================================================

    ====================================
    Detailed Report for Clock: Top|CLK
    ====================================

    Starting Points with Worst Slack
    ********************************

                  Starting                                                        Arrival
    Instance      Reference     Type        Pin     Net                           Time        Slack
                  Clock
    -------------------------------------------------------------------------------------------------
    encrypted     Top|CLK       FD1P3IX     Q       eLLu99aJ5Bmnc41207J           0.946       995.518
    encrypted     Top|CLK       FD1P3IX     Q       o1sr1Dpc5y5BnGpsJpibGI3       0.863       995.563
    encrypted     Top|CLK       FD1P3IX     Q       o1sr1Dpc5y5BnGpsJpibHbJ       0.838       995.588
    encrypted     Top|CLK       FD1P3IX     Q       c8pHcEsIxIrb                  0.883       995.895
    encrypted     Top|CLK       FD1P3IX     Q       c8pHcEsIxIrb                  0.883       995.895
    encrypted     Top|CLK       FD1P3IX     Q       c8pHcEsIxIrb                  0.883       995.895
    encrypted     Top|CLK       FD1P3IX     Q       c8pHcEsIxIrb                  0.883       995.895
    encrypted     Top|CLK       FD1P3IX     Q       by1JGvCJzf7h084gCtcbCwbI3     0.838       995.941
    encrypted     Top|CLK       FD1P3IX     Q       by1JGvCJzf7h084gCtcbCwbI3     0.838       995.941
    encrypted     Top|CLK       FD1P3IX     Q       by1JGvCJzf7h084gCtcbCwbI3     0.838       995.941
    =================================================================================================

    Ending Points with Worst Slack
    ******************************

                  Starting                                                                     Required
    Instance      Reference     Type        Pin     Net                                        Time         Slack
                  Clock
    ---------------------------------------------------------------------------------------------------------------
    encrypted     Top|CLK       FD1P3IX     D       bbJitcd5xrk5BIHJlIu0yyD21KrJ               999.789      995.518
    encrypted     Top|CLK       FD1P3IX     D       bbJitcd5xrk5BIHJlIu0yyD21Kxn               999.789      995.518
    encrypted     Top|CLK       FD1P3IX     D       nG0FpAGr2fkAKAG0nfun9Dn                    999.789      995.561
    encrypted     Top|CLK       FD1P3IX     SP      ba8eq0toDDLcz2xAv8Axeuga65ajemFwH6Ficb     999.817      995.563
    encrypted     Top|CLK       FD1P3IX     SP      ba8eq0toDDLcz2xAv8Axeuga65ajemFwH6Ficb     999.817      995.563
    encrypted     Top|CLK       FD1P3IX     SP      ba8eq0toDDLcz2xAv8Axeuga65ajemFwH6Ficb     999.817      995.563
    encrypted     Top|CLK       FD1P3IX     SP      ba8eq0toDDLcz2xAv8Axeuga65ajemFwH6Ficb     999.817      995.563
    encrypted     Top|CLK       FD1P3IX     SP      ba8eq0toDDLcz2xAv8Axeuga65ajemFwH6Ficb     999.817      995.563
    encrypted     Top|CLK       FD1P3IX     SP      ba8eq0toDDLcz2xAv8Axeuga65ajemFwH6Ficb     999.817      995.563
    encrypted     Top|CLK       FD1P3IX     SP      HG50HH61gwvaf2n3u9E67E2qll8                999.817      995.613
    ===============================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.211
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         999.789

        - Propagation time:                      4.271
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 995.518

        Number of logic level(s):                6
        Starting point:                          encrypted / Q
        Ending point:                            encrypted / D
        The start point is clocked by            Top|CLK [rising] (rise=0.000 fall=500.000 period=1000.000) on pin CK
        The end   point is clocked by            Top|CLK [rising] (rise=0.000 fall=500.000 period=1000.000) on pin CK

    Instance / Net                                          Pin      Pin               Arrival     No. of
    Name                                        Type        Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    encrypted                                   FD1P3IX     Q        Out     0.946     0.946 r     -
    eLLu99aJ5Bmnc41207J                         Net         -        -       -         -           20
    encrypted                                   LUT4        C        In      0.000     0.946 r     -
    encrypted                                   LUT4        Z        Out     0.523     1.468 r     -
    fh7plB                                      Net         -        -       -         -           1
    encrypted                                   LUT4        A        In      0.000     1.468 r     -
    encrypted                                   LUT4        Z        Out     0.683     2.151 f     -
    fh7pbf                                      Net         -        -       -         -           9
    encrypted                                   LUT4        A        In      0.000     2.151 f     -
    encrypted                                   LUT4        Z        Out     0.685     2.837 r     -
    bbHKib8byGBwLrz9njvAq3LbKx8u                Net         -        -       -         -           10
    encrypted                                   LUT4        B        In      0.000     2.837 r     -
    encrypted                                   LUT4        Z        Out     0.523     3.360 r     -
    gm6oilms56esaJlkgjxKcdbKf4cw2i7Jo1rc5hr     Net         -        -       -         -           1
    encrypted                                   LUT4        B        In      0.000     3.360 r     -
    encrypted                                   LUT4        Z        Out     0.568     3.928 f     -
    qdwhak0JK8jpuFixCELlsrd                     Net         -        -       -         -           2
    encrypted                                   LUT4        A        In      0.000     3.928 f     -
    encrypted                                   LUT4        Z        Out     0.343     4.271 f     -
    bbJitcd5xrk5BIHJlIu0yyD21KrJ                Net         -        -       -         -           1
    encrypted                                   FD1P3IX     D        In      0.000     4.271 f     -
    =========================================================================================================

    ====================================
    Detailed Report for Clock: Top|jtck_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                  Starting                                                          Arrival
    Instance      Reference                   Type        Pin     Net               Time        Slack
                  Clock
    ---------------------------------------------------------------------------------------------------
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       ngfjhruLu9jrb     1.036       994.426
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAenxn        1.006       994.446
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAemxn        0.998       994.455
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAenrJ        0.964       994.489
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAemDn        0.946       994.507
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       cmes8uaw9d23      0.923       994.529
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       cmes8uaw9d7J      0.883       994.569
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAem23        1.000       994.976
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       umDyvAem7J        0.981       994.995
    encrypted     Top|jtck_inferred_clock     FD1P3DX     Q       cmes8uaw9dDn      0.938       995.028
    ===================================================================================================

    Ending Points with Worst Slack
    ******************************

                     Starting                                                                                  Required
    Instance         Reference                   Type        Pin            Net                                Time         Slack
                     Clock
    -------------------------------------------------------------------------------------------------------------------------------
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              eF29acFIhhC9Hpr3ECv                999.789      994.426
    encrypted        Top|jtck_inferred_clock     FD1P3BX     D              iysCylwjcK5ibG7J                   999.789      994.949
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              3EEGnDuv6vAaw6eon7tLKmpbaJrG7J     999.789      995.087
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              3EEGnDuv6vAaw6eon7tLKmpbaJrGDn     999.789      995.087
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              3EEGnDuv6vAaw6eon7tLKmpbaJrGI3     999.789      995.087
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              3EEGnDuv6vAaw6eon7tLKmpbaJrHbJ     999.789      995.087
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              3EEGnDuv6vAaw6eon7tLKmpbaJrHhn     999.789      995.087
    jtaghub_inst     Top|jtck_inferred_clock     JTAGH19     ER2_TDO[0]     er2_tdo0                           1000.000     995.503
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              f2242iptfGG54FCF82lLaCym5Jhxn      999.789      995.515
    encrypted        Top|jtck_inferred_clock     FD1P3DX     D              f2242iptfGG54FCF82lLaCym5Jh23      999.789      995.515
    ===============================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.211
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         999.789

        - Propagation time:                      5.363
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     994.426

        Number of logic level(s):                8
        Starting point:                          encrypted / Q
        Ending point:                            encrypted / D
        The start point is clocked by            Top|jtck_inferred_clock [falling] (rise=0.000 fall=500.000 period=1000.000) on pin CK
        The end   point is clocked by            Top|jtck_inferred_clock [falling] (rise=0.000 fall=500.000 period=1000.000) on pin CK

    Instance / Net                                   Pin      Pin               Arrival     No. of
    Name                                 Type        Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------
    encrypted                            FD1P3DX     Q        Out     1.036     1.036 r     -
    ngfjhruLu9jrb                        Net         -        -       -         -           95
    encrypted                            LUT4        A        In      0.000     1.036 r     -
    encrypted                            LUT4        Z        Out     0.736     1.772 f     -
    brrsbLf6AoEnFss                      Net         -        -       -         -           29
    encrypted                            LUT4        B        In      0.000     1.772 f     -
    encrypted                            LUT4        Z        Out     0.523     2.295 r     -
    dnBjctpo03d6ryGzG1Im3uAdiFA4rom3     Net         -        -       -         -           1
    encrypted                            LUT4        B        In      0.000     2.295 r     -
    encrypted                            LUT4        Z        Out     0.523     2.818 r     -
    nggn2AjrtDIra                        Net         -        -       -         -           1
    encrypted                            LUT4        B        In      0.000     2.818 r     -
    encrypted                            LUT4        Z        Out     0.523     3.341 r     -
    nggn2AjrtDIrb                        Net         -        -       -         -           1
    encrypted                            LUT4        A        In      0.000     3.341 r     -
    encrypted                            LUT4        Z        Out     0.523     3.864 r     -
    nggn2AjrtDIre                        Net         -        -       -         -           1
    encrypted                            LUT4        B        In      0.000     3.864 r     -
    encrypted                            LUT4        Z        Out     0.633     4.497 r     -
    hav1h5                               Net         -        -       -         -           4
    encrypted                            LUT4        A        In      0.000     4.497 r     -
    encrypted                            LUT4        Z        Out     0.523     5.020 r     -
    jfyhuHcfopfbALDIbzt21k9Bl6           Net         -        -       -         -           1
    encrypted                            LUT4        C        In      0.000     5.020 r     -
    encrypted                            LUT4        Z        Out     0.343     5.363 r     -
    eF29acFIhhC9Hpr3ECv                  Net         -        -       -         -           1
    encrypted                            FD1P3DX     D        In      0.000     5.363 r     -
    ==================================================================================================

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                             Starting                                                                                      Arrival
    Instance                                                                 Reference     Type        Pin              Net                                                Time        Slack
                                                                             Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    jtaghub_inst                                                             System        JTAGH19     JCE2             jce2                                               0.000       995.462
    jtaghub_inst                                                             System        JTAGH19     JSHIFT           jshift                                             0.000       995.462
    jtaghub_inst                                                             System        JTAGH19     IP_ENABLE[0]     ip_enable[0]                                       0.000       996.028
    encrypted                                                                System        WIDEFN9     Z                fh7plC                                             0.000       996.463
    encrypted                                                                System        WIDEFN9     Z                fh7plF                                             0.000       996.463
    top_reveal_coretop_instance.core0.trig_u.tu_0_rd_dout_tu_RNIJL1T2[0]     System        WIDEFN9     Z                N_131                                              0.000       997.599
    encrypted                                                                System        WIDEFN9     Z                fh7pgz                                             0.000       997.767
    encrypted                                                                System        WIDEFN9     Z                fh7pl8                                             0.000       997.767
    encrypted                                                                System        WIDEFN9     Z                bHkKCEKFJ91qEjLJqgfdrKhqK9aJkcwaI7CrCrlwkkjhn      0.000       997.877
    encrypted                                                                System        WIDEFN9     Z                kg0z5kzL9J7FCvp7Ca1bLChkzkBJwgmkbpizz50kLGC4xn     0.000       997.877
    ==========================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                     Starting                                                                   Required
    Instance         Reference     Type        Pin            Net                               Time         Slack
                     Clock
    ----------------------------------------------------------------------------------------------------------------
    encrypted        System        FD1P3DX     D              eF29acFIhhC9Hpr3ECv               999.789      995.462
    encrypted        System        FD1P3BX     D              iysCylwjcK5ibG7J                  999.789      995.986
    encrypted        System        FD1P3IX     D              bbJitcd5xrk5BIHJlIu0yyD21KrJ      999.789      996.463
    encrypted        System        FD1P3IX     D              bbJitcd5xrk5BIHJlIu0yyD21Kxn      999.789      996.463
    encrypted        System        FD1P3IX     D              nG0FpAGr2fkAKAG0nfun9Dn           999.789      996.506
    jtaghub_inst     System        JTAGH19     ER2_TDO[0]     er2_tdo0                          1000.000     996.539
    encrypted        System        FD1P3DX     D              f2242iptfGG54FCF82lLaCym5Jhxn     999.789      996.881
    encrypted        System        FD1P3DX     D              f2242iptfGG54FCF82lLaCym5Jh23     999.789      996.881
    encrypted        System        FD1P3IX     D              eLLu99aJ5Bmnc417twq               999.789      996.986
    encrypted        System        FD1P3IX     D              eLLu99aJ5Bmnc417twr               999.789      996.986
    ================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.211
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         999.789

        - Propagation time:                      4.327
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 995.462

        Number of logic level(s):                8
        Starting point:                          jtaghub_inst / JCE2
        Ending point:                            encrypted / D
        The start point is clocked by            System [rising]
        The end   point is clocked by            Top|jtck_inferred_clock [falling] (rise=0.000 fall=500.000 period=1000.000) on pin CK

    Instance / Net                                   Pin      Pin               Arrival     No. of
    Name                                 Type        Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------
    jtaghub_inst                         JTAGH19     JCE2     Out     0.000     0.000 r     -
    jce2                                 Net         -        -       -         -           12
    encrypted                            LUT4        C        In      0.000     0.000 r     -
    encrypted                            LUT4        Z        Out     0.736     0.736 r     -
    brrsbLf6AoEnFss                      Net         -        -       -         -           29
    encrypted                            LUT4        B        In      0.000     0.736 r     -
    encrypted                            LUT4        Z        Out     0.523     1.258 f     -
    dnBjctpo03d6ryGzG1Im3uAdiFA4rom3     Net         -        -       -         -           1
    encrypted                            LUT4        B        In      0.000     1.258 f     -
    encrypted                            LUT4        Z        Out     0.523     1.782 f     -
    nggn2AjrtDIra                        Net         -        -       -         -           1
    encrypted                            LUT4        B        In      0.000     1.782 f     -
    encrypted                            LUT4        Z        Out     0.523     2.304 f     -
    nggn2AjrtDIrb                        Net         -        -       -         -           1
    encrypted                            LUT4        A        In      0.000     2.304 f     -
    encrypted                            LUT4        Z        Out     0.523     2.828 f     -
    nggn2AjrtDIre                        Net         -        -       -         -           1
    encrypted                            LUT4        B        In      0.000     2.828 f     -
    encrypted                            LUT4        Z        Out     0.633     3.461 f     -
    hav1h5                               Net         -        -       -         -           4
    encrypted                            LUT4        A        In      0.000     3.461 f     -
    encrypted                            LUT4        Z        Out     0.523     3.983 r     -
    jfyhuHcfopfbALDIbzt21k9Bl6           Net         -        -       -         -           1
    encrypted                            LUT4        C        In      0.000     3.983 r     -
    encrypted                            LUT4        Z        Out     0.343     4.327 r     -
    eF29acFIhhC9Hpr3ECv                  Net         -        -       -         -           1
    encrypted                            FD1P3DX     D        In      0.000     4.327 r     -
    ==================================================================================================

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    @W:MT447 : reveal_constraint.sdc(2) | Timing constraint (to [get_clocks rvltck]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 242MB)

    Finished timing report (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 238MB peak: 242MB)

    ---------------------------------------
    Resource Usage Report
    Part: lfcpnx_100-9

    Register bits: 1044 of 79872 (1%)
    PIC Latch:       0
    I/O cells:       5

    Details:
    CCU2:           124
    DCC:            1
    DPR16X4:        40
    FD1P3BX:        32
    FD1P3DX:        335
    FD1P3IX:        668
    FD1P3JX:        5
    GSR:            1
    IB:             1
    INV:            10
    JTAGH19:        1
    LUT4:           997
    OB:             4
    OFD1P3IX:       4
    OSCA:           1
    VHI:            23
    VLO:            23
    WIDEFN9:        62

    Resource Usage inside macros:
    Registers: 0
    LUTs: 0
    EBRs: 0
    LRAMs: 0
    DSPs: 0
    Distributed RAMs: 0
    Carry Chains: 0
    Blackboxes: 0

    Mapping Summary:
    Total number of registers: 1044 + 0 = 1044 of 79872 (1.31%)
    Total number of LUTs: 997 + 0 = 997
    Total number of EBRs: 0 + 0 = 0 of 208 (0.00%)
    Total number of LRAMs: 0 + 0 = 0 of 7 (0.00%)
    Total number of DSPs: 0 + 0 = 0 of 156 (0.00%)
    Total number of Distributed RAMs: 40 + 0 = 40
    Total number of Carry Chains: 124 + 0 = 124
    Total number of BlackBoxes: 50 + 0 = 50
    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 242MB)

    Process took 0h:00m:08s realtime, 0h:00m:01s cputime
    # Wed Nov 29 09:20:40 2023

    ###########################################################]

`