                             Lattice Mapping Report File
    Design:  DPRAM1
    Family:  LFCPNX
    Device:  LFCPNX-100
    Package: ASG256
    Performance Grade:  9_High-Performance_1.0V

    Mapper:    version Radiant Software (64-bit) 2023.1.1.200.1
    Mapped on: Mon Nov 20 10:35:09 2023

    Design Information

    Command line:   map -i LAB06_impl_1_syn.udb -o LAB06_impl_1_map.udb -mp
         LAB06_impl_1.mrp -hierrpt -gui

    Design Summary
       Number of registers:        18450 out of 80349 (23%)
          Number of SLICE         registers: 18450 out of 79872 (23%)
          Number of PIO Input     registers:    0 out of   159 (0%)
          Number of PIO Output    registers:    0 out of   159 (0%)
          Number of PIO Tri-State registers:    0 out of   159 (0%)
       Number of LUT4s:            13365 out of 79872 (17%)
          Number used as logic LUT4s:                       13365
          Number used as distributed RAM:                      0 (6 per 16X4 RAM)
          Number used as ripple logic:                         0 (2 per CCU2)
       Number of PIOs used/reserved:   70 out of   159 (44%)
          Number of PIOs reserved:      7 (per sysConfig and/or prohibit constraint)
          Number of PIOs used:         63
            Number of PIOs used for single ended IO:        63
            Number of PIO pairs used for differential IO:    0
            Number allocated to regular speed PIOs:    63 out of   75 (84%)
            Number allocated to high speed PIOs:        0 out of   84 (0%)
       Number of Dedicated IO used for ADC/PCS/PCIE:    0 out of   34 (0%)
       Number of IDDR/ODDR/TDDR functions used:      0 out of   402 (0%)
       Number of IOs using at least one DDR function: 0 (0 differential)
       Number of Block RAMs:          0 out of 208 (0%)
       Number of Large RAMs:          0 out of 7 (0%)
       Number of Logical DSP Functions:
          Number of Pre-Adders (9+9):    0 out of 312 (0%)
          Number of Multipliers (18x18): 0 out of 156 (0%)
             Number of 9X9:        0 (1 18x18 = 2   9x9)
             Number of 18x18:      0 (1 18x18 = 1 18x18)
             Number of 18x36:      0 (2 18x18 = 1 18x36)
             Number of 36x36:      0 (4 18x18 = 1 36x36)
          Number of 54-bit Accumulators: 0 out of 78 (0%)
          Number of 18-bit Registers:    0 out of 312 (0%)
       Number of Physical DSP Components:
          Number of PREADD9:             0 out of 312 (0%)
          Number of MULT9:               0 out of 312 (0%)
          Number of MULT18:              0 out of 156 (0%)
          Number of MULT18X36:           0 out of 78 (0%)
          Number of MULT36:              0 out of 39 (0%)
          Number of ACC54:               0 out of 78 (0%)
          Number of REG18:               0 out of 312 (0%)
       Number of ALUREGs:             0 out of 1 (0%)
       Number of PLLs:                0 out of 4 (0%)
       Number of DDRDLLs:             0 out of 2 (0%)
       Number of DLLDELs:             0 out of 10 (0%)

       Number of DQSs:                0 out of 11 (0%)
       Number of DCSs:                0 out of 2 (0%)
       Number of DCCs:                0 out of 62 (0%)
       Number of PCLKDIVs:            0 out of 2 (0%)
       Number of ECLKDIVs:            0 out of 12 (0%)
       Number of ECLKSYNCs:           0 out of 12 (0%)
       Number of ADC Blocks:          0 out of 1 (0%)
       Number of SGMIICDRs:           0 out of 2 (0%)
       Number of PMUs:                0 out of 1 (0%)
       Number of BNKREF18s:           0 out of 3 (0%)
       Number of BNKREF33s:           0 out of 5 (0%)
       Number of I2CFIFOs:            0 out of 1 (0%)
       Number of Oscillators:         0 out of 1 (0%)
       Number of GSR:                 1 out of 1 (100%)
       Number of Cryptographic Block: 0 out of 1 (0%)
       Number of Config IP:           0 out of 1 (0%)
                     TSALL:           0 out of 1 (0%)
       Number of JTAG:                0 out of 1 (0%)
       Number of SED:                 0 out of 1 (0%)
       Number of PCSs:                0 out of 2 (0%)
       Number of PCIE Link Layers:    0 out of 1 (0%)
       Number of Clocks:  2
          Net wr_clk_i_c: 18432 loads, 18432 rising, 0 falling (Driver: Port
         wr_clk_i)
          Net rd_clk_i_c: 18 loads, 18 rising, 0 falling (Driver: Port rd_clk_i)
       Number of Clock Enables:  1025
          Net wr_clk_i_c_enable_10633: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10501: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10211: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9568: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10462: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9195: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10055: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9772: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10550: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8994: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10262: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9480: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4508: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10413: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9258: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5269: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2832: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3516: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17186: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16359: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15594: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14849: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10005: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9825: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8940: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10147: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9651: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9129: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10094: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9716: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9059: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_10313: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9427: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10361: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9311: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9944: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9890: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10587: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8873: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8664: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8280: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7569: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8583: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7070: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8108: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7786: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8732: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6817: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14047: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12546: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11818: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13285: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9606: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10391: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8841: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11114: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6676: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7386: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5965: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8099: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15486: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8333: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17233: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13669: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18031: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7493: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9530: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5059: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11570: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2475: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2474: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2477: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2487: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2489: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2488: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7393: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18417: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2473: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2472: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2471: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2478: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2470: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2469: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2468: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2467: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2479: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2466: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2920: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_2456: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2444: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2439: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2447: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2436: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2443: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2440: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8481: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2435: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2455: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2445: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2438: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2446: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2437: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2442: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2441: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2457: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2465: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2434: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2464: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2853: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2463: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2495: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2462: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2494: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2461: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2493: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2480: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2448: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2460: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2492: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7139: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2459: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2491: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2458: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2490: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7276: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9376: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11349: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13486: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15283: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17082: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17980: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4195: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3447: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4406: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5204: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5896: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6615: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7312: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8030: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8775: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9528: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10309: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11049: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11758: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12474: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_13214: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13977: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8042: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14767: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15527: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2393: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2425: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4809: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2481: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2449: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2485: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2453: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2484: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2452: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2483: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2451: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2482: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2450: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2431: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2424: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2412: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2430: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2407: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2420: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2415: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2432: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2404: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7852: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2426: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2411: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2429: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2408: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2419: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2416: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2403: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2423: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2413: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2406: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2421: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2414: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2405: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2427: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2410: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2428: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2409: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2418: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2417: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2433: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2402: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2399: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2793: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3051: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2398: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2946: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3216: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3112: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2400: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_2880: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2394: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3031: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2397: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2966: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3196: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3133: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2858: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3255: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3072: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2925: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3235: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3092: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2902: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2395: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3011: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2396: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2989: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3175: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3154: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2401: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2813: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18432: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17587: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18414: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18397: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16886: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6748: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16914: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16937: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16965: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16988: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17019: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17046: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17072: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17102: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17131: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17159: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17207: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17228: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17252: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17274: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17297: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17321: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17343: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17366: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17391: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17416: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17442: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17463: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17490: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17511: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17535: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17562: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16832: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16706: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16682: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_8225: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16260: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16781: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16191: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16124: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16557: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16428: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16634: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16337: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16506: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16479: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16286: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16805: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16169: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16529: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16456: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16308: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16146: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16731: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16660: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16238: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16757: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16217: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16859: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16103: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16580: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16407: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16611: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16380: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16027: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7646: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16001: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15780: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15972: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15709: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15683: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16083: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15501: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15851: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15549: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15338: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15407: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15428: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15925: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15829: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15637: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16053: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15455: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15899: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15806: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15614: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15755: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15950: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15731: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15662: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15476: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15875: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_15573: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15359: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15383: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15273: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15119: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15184: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15098: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14902: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14795: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15293: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14989: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14690: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15252: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14611: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14588: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15204: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15035: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15315: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14932: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14744: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15227: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15055: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14962: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14716: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15160: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15139: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15075: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14877: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14818: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15015: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14662: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6987: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14635: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14561: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14490: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14116: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14286: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13857: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14410: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13999: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14387: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13954: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14512: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14138: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14258: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13831: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14441: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14021: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14359: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13933: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14537: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14189: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14210: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13780: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14090: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14309: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13883: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_14464: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14068: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14336: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8172: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13913: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14167: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14237: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13802: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13706: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13585: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13379: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13729: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13168: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13561: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13403: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13146: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13659: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13306: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13681: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13258: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13492: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13468: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13082: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13057: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13610: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13357: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13189: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13539: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13424: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13755: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13123: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13636: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7718: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13331: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13237: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13513: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13444: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13103: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13034: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12969: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12616: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12845: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12405: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12642: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12825: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12379: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13014: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12905: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12495: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12744: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12314: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12928: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12665: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12796: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12357: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12990: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12949: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_12885: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12693: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12766: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12337: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12572: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12450: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12594: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12865: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12426: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12523: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12715: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12292: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12219: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12081: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11839: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12196: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11687: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12016: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11902: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12241: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11614: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12102: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11798: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12171: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11711: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11993: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11925: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11593: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12058: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11862: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11662: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12036: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6902: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11882: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11640: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12126: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11778: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12150: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11738: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11968: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11947: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12270: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11569: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11504: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11370: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11134: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11482: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10985: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11305: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11203: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11525: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10926: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11391: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11091: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11459: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11006: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11284: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_11222: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10904: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11348: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11155: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8394: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10965: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11327: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11182: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10945: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11414: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11069: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11437: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11026: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11263: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11242: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11545: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10881: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10820: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10702: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10418: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10801: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10236: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10641: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10494: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10842: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10163: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10722: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10367: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10781: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10258: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10608: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10524: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10137: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10683: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7342: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10442: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10208: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10665: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10470: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10185: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10741: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10337: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10761: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10286: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10578: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10547: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10861: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10116: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10034: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9884: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9627: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10007: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9454: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9813: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9695: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10062: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9377: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_9910: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9582: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9983: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9477: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9790: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9717: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8444: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9355: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9862: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9648: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9428: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9841: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9673: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9404: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9932: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9559: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9960: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9505: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9764: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9742: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10086: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9332: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9256: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9117: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8863: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9234: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8707: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9051: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8932: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9285: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8641: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9140: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8817: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9210: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8729: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9031: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7211: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8956: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8621: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9096: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8887: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8684: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9072: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8910: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8662: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9165: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8796: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9186: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8755: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9006: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8980: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_9307: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8598: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8537: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8390: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8121: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8514: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_7964: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8317: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8198: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8556: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7893: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8418: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8078: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8495: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7972: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7985: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8289: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8220: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7867: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8367: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8147: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7944: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8340: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8169: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7916: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8441: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8052: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8472: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8009: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8268: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8241: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8576: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7845: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7776: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7642: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7408: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7753: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7243: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7575: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7469: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7798: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7175: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7666: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7907: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7357: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7730: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7266: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7554: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7489: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7152: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7620: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7427: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7218: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7597: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7449: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7197: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7688: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7335: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7709: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7287: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7534: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7511: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7823: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_7132: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7063: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6934: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6699: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7042: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6554: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6874: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6762: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7084: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_8805: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6491: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6955: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6656: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7018: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6575: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6854: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6785: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6471: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6914: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6721: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6533: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6894: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6741: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6512: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6978: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6637: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6998: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6595: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6829: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6807: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_7110: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6452: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6392: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6263: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5991: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6373: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5828: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6184: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6662: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6063: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6411: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5761: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6287: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5943: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6354: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5848: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6161: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6085: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5737: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6235: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6014: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5807: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6206: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6042: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5783: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6317: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5917: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_6335: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5873: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6133: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6111: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6433: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5710: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5637: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5509: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5289: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5616: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6313: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5143: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5446: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5347: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5662: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5082: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5530: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5247: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5596: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5165: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5427: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5368: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5058: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5482: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5309: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5123: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5464: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5328: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5103: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5551: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5225: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5576: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5185: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5408: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5389: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5689: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5038: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4971: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4846: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6005: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4542: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4949: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4304: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4781: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4644: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4996: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4202: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4866: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4474: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4927: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4338: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4761: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4678: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4168: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4824: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4576: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4270: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_4801: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4610: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4236: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4886: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4440: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4906: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4372: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4736: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4712: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5017: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4134: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5144: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4032: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3828: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3538: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3998: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3370: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3726: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3605: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4066: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3314: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3862: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3491: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3964: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3398: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3694: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3626: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3295: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3794: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3560: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3352: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3760: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3584: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3333: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3896: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3469: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3930: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3421: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3672: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3646: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6276: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4100: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3276: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3193: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3668: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4059: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3322: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4297: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3787: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3957: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3108: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4399: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3597: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4127: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3409: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4263: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3821: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_3923: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4433: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3719: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4025: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4331: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3753: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3991: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4365: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3529: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4161: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3462: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4229: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3855: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3889: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_3002: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4467: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4569: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18236: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18048: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4603: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17929: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18184: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18099: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4535: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17878: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18243: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18014: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4637: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17946: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18167: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18116: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17861: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18218: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18065: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17912: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18201: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18082: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17895: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18295: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5806: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4705: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5486: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6459: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17997: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4671: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17963: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18150: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18133: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4501: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17844: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17793: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17691: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17300: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17776: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16946: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17640: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17483: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_17810: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16806: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17708: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17163: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17759: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16996: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17623: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17538: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16752: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17674: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17367: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16894: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17657: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17419: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16855: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17725: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17128: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17742: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17043: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17606: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17589: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_17827: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16701: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16539: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16198: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15537: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16487: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15046: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16023: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15741: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16589: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14896: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16264: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15430: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16436: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15141: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15973: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15793: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14856: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16130: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15618: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14978: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16063: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15684: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14942: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16318: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15363: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16381: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15215: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15912: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_15859: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_16638: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14808: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14668: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14352: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13724: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14619: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_13295: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18346: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14180: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13877: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14708: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13089: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14401: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13606: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14565: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13349: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14129: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13928: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6057: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13022: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14299: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13775: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13230: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14247: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13827: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13164: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14448: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13552: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14504: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_13418: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14074: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14009: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_14759: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12941: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12741: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12398: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11634: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4978: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12687: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11106: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12209: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11851: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12789: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10824: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12465: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11498: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12636: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6226: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11174: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12142: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11927: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18278: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2454: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2422: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_2486: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4093: 18 loads, 18 SLICEs
          Net rd_clk_i_c_enable_18: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5748: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5553: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18363: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5942: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5234: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18312: 18 loads, 18 SLICEs

          Net wr_clk_i_c_enable_5883: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5348: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18329: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6123: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_4895: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6174: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18261: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5685: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_5625: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_6560: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_18380: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10704: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12330: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11699: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11022: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12261: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11754: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_10918: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12520: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11428: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12583: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11264: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12076: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_11995: 18 loads, 18 SLICEs
          Net wr_clk_i_c_enable_12843: 18 loads, 18 SLICEs
       Number of LSRs:  0
       Top 10 highest fanout non-clock nets:
          Net rd_addr_i_c_0: 9216 loads
          Net rd_addr_i_c_1: 4608 loads
          Net rd_addr_i_c_2: 2304 loads
          Net rd_addr_i_c_3: 1152 loads
          Net wr_data_i_c_12: 1024 loads
          Net wr_data_i_c_13: 1024 loads
          Net wr_data_i_c_14: 1024 loads
          Net wr_data_i_c_15: 1024 loads
          Net wr_data_i_c_16: 1024 loads
          Net wr_data_i_c_17: 1024 loads

       Number of warnings:  0
       Number of errors:    0

       Number of LSRs:  0
       Top 10 highest fanout non-clock nets:
          Net rd_addr_i_c_0: 9216 loads
          Net rd_addr_i_c_1: 4608 loads
          Net rd_addr_i_c_2: 2304 loads
          Net rd_addr_i_c_3: 1152 loads
          Net wr_data_i_c_12: 1024 loads
          Net wr_data_i_c_13: 1024 loads
          Net wr_data_i_c_14: 1024 loads
          Net wr_data_i_c_15: 1024 loads
          Net wr_data_i_c_16: 1024 loads
          Net wr_data_i_c_17: 1024 loads

       Number of warnings:  0
       Number of errors:    0

    Design Errors/Warnings

       No errors or warnings present.

    IO (PIO) Attributes

    +---------------------+-----------+-----------+-------+-------+-----------+
    | IO Name             | Direction | Levelmode |  IO   |  IO   | Special   |
    |                     |           |  IO_TYPE  |  REG  |  DDR  | IO Buffer |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[17]       | OUTPUT    |           |       |       |           |

    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[0]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[1]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[2]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[3]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[4]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[5]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[6]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[7]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[8]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[9]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[10]       | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[11]       | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[12]       | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[13]       | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[14]       | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[15]       | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[16]       | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_data_i[17]       | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rst_i               | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_clk_en_i         | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_clk_en_i         | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_clk_i            | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_clk_i            | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_en_i             | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_en_i             | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_addr_i[0]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_addr_i[1]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_addr_i[2]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+

    | rd_addr_i[3]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_addr_i[4]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_addr_i[5]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_addr_i[6]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_addr_i[7]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_addr_i[8]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_addr_i[9]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_addr_i[0]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_addr_i[1]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_addr_i[2]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_addr_i[3]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_addr_i[4]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_addr_i[5]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_addr_i[6]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_addr_i[7]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_addr_i[8]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | wr_addr_i[9]        | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[0]        | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[1]        | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[2]        | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[3]        | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[4]        | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[5]        | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[6]        | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[7]        | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[8]        | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[9]        | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[10]       | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[11]       | OUTPUT    |           |       |       |           |

    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[12]       | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[13]       | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[14]       | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[15]       | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | rd_data_o[16]       | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+

    Removed logic

    Block i1 was optimized away.
    Block i55487 was optimized away.
    Block wr_data_i_pad[0]_lut_buf_1 was optimized away.
    Block wr_data_i_pad[0]_lut_buf_2 was optimized away.
    Block wr_data_i_pad[1]_lut_buf_3 was optimized away.
    Block wr_data_i_pad[1]_lut_buf_4 was optimized away.
    Block wr_data_i_pad[2]_lut_buf_5 was optimized away.
    Block wr_data_i_pad[2]_lut_buf_6 was optimized away.
    Block wr_data_i_pad[3]_lut_buf_7 was optimized away.
    Block wr_data_i_pad[3]_lut_buf_8 was optimized away.
    Block wr_data_i_pad[4]_lut_buf_9 was optimized away.
    Block wr_data_i_pad[4]_lut_buf_10 was optimized away.
    Block wr_data_i_pad[5]_lut_buf_11 was optimized away.
    Block wr_data_i_pad[5]_lut_buf_12 was optimized away.
    Block wr_data_i_pad[6]_lut_buf_13 was optimized away.
    Block wr_data_i_pad[6]_lut_buf_14 was optimized away.
    Block wr_data_i_pad[7]_lut_buf_15 was optimized away.
    Block wr_data_i_pad[7]_lut_buf_16 was optimized away.
    Block wr_data_i_pad[8]_lut_buf_17 was optimized away.
    Block wr_data_i_pad[8]_lut_buf_18 was optimized away.
    Block wr_data_i_pad[9]_lut_buf_19 was optimized away.
    Block wr_data_i_pad[9]_lut_buf_20 was optimized away.
    Block wr_data_i_pad[10]_lut_buf_21 was optimized away.
    Block wr_data_i_pad[10]_lut_buf_22 was optimized away.
    Block wr_data_i_pad[11]_lut_buf_23 was optimized away.
    Block wr_data_i_pad[11]_lut_buf_24 was optimized away.
    Block wr_data_i_pad[12]_lut_buf_25 was optimized away.
    Block wr_data_i_pad[12]_lut_buf_26 was optimized away.
    Block wr_data_i_pad[13]_lut_buf_27 was optimized away.
    Block wr_data_i_pad[13]_lut_buf_28 was optimized away.
    Block wr_data_i_pad[14]_lut_buf_29 was optimized away.
    Block wr_data_i_pad[14]_lut_buf_30 was optimized away.
    Block wr_data_i_pad[15]_lut_buf_31 was optimized away.
    Block wr_data_i_pad[15]_lut_buf_32 was optimized away.
    Block wr_data_i_pad[16]_lut_buf_33 was optimized away.
    Block wr_data_i_pad[16]_lut_buf_34 was optimized away.
    Block wr_data_i_pad[17]_lut_buf_35 was optimized away.
    Block wr_data_i_pad[17]_lut_buf_36 was optimized away.
    Block rd_addr_i_pad[0]_lut_buf_37 was optimized away.
    Block rd_addr_i_pad[0]_lut_buf_38 was optimized away.
    Block rd_addr_i_pad[0]_lut_buf_39 was optimized away.
    Block rd_addr_i_pad[0]_lut_buf_40 was optimized away.

    Block rd_addr_i_pad[0]_lut_buf_41 was optimized away.
    Block rd_addr_i_pad[0]_lut_buf_42 was optimized away.
    Block rd_addr_i_pad[0]_lut_buf_43 was optimized away.
    Block rd_addr_i_pad[0]_lut_buf_44 was optimized away.
    Block rd_addr_i_pad[0]_lut_buf_45 was optimized away.
    Block rd_addr_i_pad[0]_lut_buf_46 was optimized away.
    Block rd_addr_i_pad[1]_lut_buf_47 was optimized away.
    Block rd_addr_i_pad[1]_lut_buf_48 was optimized away.
    Block rd_addr_i_pad[1]_lut_buf_49 was optimized away.
    Block rd_addr_i_pad[1]_lut_buf_50 was optimized away.
    Block rd_addr_i_pad[1]_lut_buf_51 was optimized away.
    Block rd_addr_i_pad[2]_lut_buf_52 was optimized away.
    Block rd_addr_i_pad[2]_lut_buf_53 was optimized away.
    Block rd_addr_i_pad[2]_lut_buf_54 was optimized away.
    Block rd_addr_i_pad[3]_lut_buf_55 was optimized away.
    Block rd_addr_i_pad[3]_lut_buf_56 was optimized away.
    Block i23722_1_lut was optimized away.
    Block i55487 was optimized away.

    GSR Usage
    ---------

    GSR Component:
       The Global Set Reset (GSR) resource has been used to implement a global reset
            of the design. The reset signal used for GSR control is 'rst_i_c'.

    GSR Property:
       The design components with GSR property set to ENABLED will respond to global
            set reset while the components with GSR property set to DISABLED will
            not.

    Constraint Summary
    ------------------

       Total number of constraints: 0
       Total number of constraints dropped: 0

    Run Time and Memory Usage
    -------------------------

       Total CPU Time: 0 secs
       Total REAL Time: 9 secs
       Peak Memory Usage: 952 MB

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995
         AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent
         Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems
         All rights reserved.
    Copyright (c) 2002-2023 Lattice Semiconductor
         Corporation,  All rights reserved.